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https://github.com/Motorhead1991/qemu.git
synced 2025-08-02 07:13:54 -06:00
tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}
Make extract and sextract "unconditional" in the sense that the opcodes are always present. Rely instead on TCG_TARGET_HAS_{s}extract_valid, now always defined. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
41736e7ce1
commit
c334de110e
14 changed files with 8 additions and 70 deletions
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@ -32,8 +32,6 @@
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#define TCG_TARGET_HAS_ctz_i32 1
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#define TCG_TARGET_HAS_ctpop_i32 0
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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@ -67,8 +65,6 @@
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#define TCG_TARGET_HAS_ctz_i64 1
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#define TCG_TARGET_HAS_ctpop_i64 0
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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@ -41,8 +41,6 @@ extern bool use_neon_instructions;
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#define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_ctpop_i32 0
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#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 1
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@ -44,8 +44,6 @@
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#define TCG_TARGET_HAS_ctz_i32 1
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#define TCG_TARGET_HAS_ctpop_i32 have_popcnt
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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@ -79,8 +77,6 @@
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#define TCG_TARGET_HAS_ctz_i64 1
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#define TCG_TARGET_HAS_ctpop_i64 have_popcnt
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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@ -16,8 +16,6 @@
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#define TCG_TARGET_HAS_div2_i32 0
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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@ -51,8 +49,6 @@
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#define TCG_TARGET_HAS_div2_i64 0
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_extr_i64_i32 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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@ -80,8 +80,6 @@ extern bool use_mips32r2_instructions;
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/* optional instructions detected at runtime */
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#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
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@ -96,8 +94,6 @@ extern bool use_mips32r2_instructions;
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
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#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
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@ -2363,10 +2363,10 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
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shr_opc = INDEX_op_shr_i32;
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neg_opc = INDEX_op_neg_i32;
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if (TCG_TARGET_extract_valid(TCG_TYPE_I32, sh, 1)) {
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uext_opc = TCG_TARGET_HAS_extract_i32 ? INDEX_op_extract_i32 : 0;
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uext_opc = INDEX_op_extract_i32;
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}
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if (TCG_TARGET_sextract_valid(TCG_TYPE_I32, sh, 1)) {
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sext_opc = TCG_TARGET_HAS_sextract_i32 ? INDEX_op_sextract_i32 : 0;
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sext_opc = INDEX_op_sextract_i32;
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}
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break;
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case TCG_TYPE_I64:
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@ -2376,10 +2376,10 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
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shr_opc = INDEX_op_shr_i64;
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neg_opc = INDEX_op_neg_i64;
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if (TCG_TARGET_extract_valid(TCG_TYPE_I64, sh, 1)) {
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uext_opc = TCG_TARGET_HAS_extract_i64 ? INDEX_op_extract_i64 : 0;
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uext_opc = INDEX_op_extract_i64;
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}
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if (TCG_TARGET_sextract_valid(TCG_TYPE_I64, sh, 1)) {
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sext_opc = TCG_TARGET_HAS_sextract_i64 ? INDEX_op_sextract_i64 : 0;
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sext_opc = INDEX_op_sextract_i64;
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}
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break;
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default:
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@ -38,8 +38,6 @@
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#define TCG_TARGET_HAS_ctz_i32 have_isa_3_00
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#define TCG_TARGET_HAS_ctpop_i32 have_isa_2_06
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_negsetcond_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 0
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@ -74,8 +72,6 @@
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#define TCG_TARGET_HAS_ctz_i64 have_isa_3_00
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#define TCG_TARGET_HAS_ctpop_i64 have_isa_2_06
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_negsetcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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@ -16,8 +16,6 @@
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#define TCG_TARGET_HAS_div2_i32 0
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#define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_deposit_i32 0
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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@ -50,8 +48,6 @@
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#define TCG_TARGET_HAS_div2_i64 0
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#define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_deposit_i64 0
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_extr_i64_i32 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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@ -47,8 +47,6 @@ extern uint64_t s390_facilities[3];
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#define TCG_TARGET_HAS_ctz_i32 0
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#define TCG_TARGET_HAS_ctpop_i32 1
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_negsetcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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@ -81,8 +79,6 @@ extern uint64_t s390_facilities[3];
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#define TCG_TARGET_HAS_ctz_i64 0
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#define TCG_TARGET_HAS_ctpop_i64 1
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_negsetcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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@ -33,8 +33,6 @@ extern bool use_vis3_instructions;
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#define TCG_TARGET_HAS_ctz_i32 0
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#define TCG_TARGET_HAS_ctpop_i32 0
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#define TCG_TARGET_HAS_deposit_i32 0
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_negsetcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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@ -68,8 +66,6 @@ extern bool use_vis3_instructions;
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#define TCG_TARGET_HAS_ctz_i64 0
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#define TCG_TARGET_HAS_ctpop_i64 0
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#define TCG_TARGET_HAS_deposit_i64 0
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_negsetcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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@ -35,8 +35,6 @@
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#define TCG_TARGET_HAS_ctz_i64 0
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#define TCG_TARGET_HAS_ctpop_i64 0
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#define TCG_TARGET_HAS_deposit_i64 0
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#define TCG_TARGET_HAS_extract_i64 0
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#define TCG_TARGET_HAS_add2_i64 0
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@ -56,16 +54,6 @@
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#ifndef TCG_TARGET_deposit_i64_valid
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#define TCG_TARGET_deposit_i64_valid(ofs, len) 1
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#endif
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#ifndef TCG_TARGET_extract_valid
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#define TCG_TARGET_extract_valid(type, ofs, len) \
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((type) == TCG_TYPE_I32 ? TCG_TARGET_HAS_extract_i32 \
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: TCG_TARGET_HAS_extract_i64)
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#endif
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#ifndef TCG_TARGET_sextract_valid
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#define TCG_TARGET_sextract_valid(type, ofs, len) \
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((type) == TCG_TYPE_I32 ? TCG_TARGET_HAS_sextract_i32 \
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: TCG_TARGET_HAS_sextract_i64)
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#endif
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/* Only one of DIV or DIV2 should be defined. */
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#if defined(TCG_TARGET_HAS_div_i32)
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12
tcg/tcg.c
12
tcg/tcg.c
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@ -2195,6 +2195,8 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
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case INDEX_op_shl_i32:
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case INDEX_op_shr_i32:
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case INDEX_op_sar_i32:
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case INDEX_op_extract_i32:
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case INDEX_op_sextract_i32:
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return true;
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case INDEX_op_negsetcond_i32:
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@ -2213,10 +2215,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
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return TCG_TARGET_HAS_rot_i32;
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case INDEX_op_deposit_i32:
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return TCG_TARGET_HAS_deposit_i32;
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case INDEX_op_extract_i32:
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return TCG_TARGET_HAS_extract_i32;
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case INDEX_op_sextract_i32:
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return TCG_TARGET_HAS_sextract_i32;
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case INDEX_op_extract2_i32:
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return TCG_TARGET_HAS_extract2_i32;
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case INDEX_op_add2_i32:
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@ -2293,6 +2291,8 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
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case INDEX_op_sar_i64:
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case INDEX_op_ext_i32_i64:
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case INDEX_op_extu_i32_i64:
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case INDEX_op_extract_i64:
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case INDEX_op_sextract_i64:
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return TCG_TARGET_REG_BITS == 64;
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case INDEX_op_negsetcond_i64:
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@ -2311,10 +2311,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
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return TCG_TARGET_HAS_rot_i64;
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case INDEX_op_deposit_i64:
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return TCG_TARGET_HAS_deposit_i64;
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case INDEX_op_extract_i64:
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return TCG_TARGET_HAS_extract_i64;
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case INDEX_op_sextract_i64:
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return TCG_TARGET_HAS_sextract_i64;
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case INDEX_op_extract2_i64:
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return TCG_TARGET_HAS_extract2_i64;
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case INDEX_op_extrl_i64_i32:
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regs[r0] = deposit32(regs[r1], pos, len, regs[r2]);
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break;
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#endif
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#if TCG_TARGET_HAS_extract_i32
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case INDEX_op_extract_i32:
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tci_args_rrbb(insn, &r0, &r1, &pos, &len);
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regs[r0] = extract32(regs[r1], pos, len);
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break;
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#endif
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#if TCG_TARGET_HAS_sextract_i32
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case INDEX_op_sextract_i32:
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tci_args_rrbb(insn, &r0, &r1, &pos, &len);
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regs[r0] = sextract32(regs[r1], pos, len);
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break;
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#endif
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case INDEX_op_brcond_i32:
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tci_args_rl(insn, tb_ptr, &r0, &ptr);
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if ((uint32_t)regs[r0]) {
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regs[r0] = deposit64(regs[r1], pos, len, regs[r2]);
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break;
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#endif
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#if TCG_TARGET_HAS_extract_i64
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case INDEX_op_extract_i64:
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tci_args_rrbb(insn, &r0, &r1, &pos, &len);
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regs[r0] = extract64(regs[r1], pos, len);
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break;
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#endif
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#if TCG_TARGET_HAS_sextract_i64
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case INDEX_op_sextract_i64:
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tci_args_rrbb(insn, &r0, &r1, &pos, &len);
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regs[r0] = sextract64(regs[r1], pos, len);
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break;
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#endif
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case INDEX_op_brcond_i64:
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tci_args_rl(insn, tb_ptr, &r0, &ptr);
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if (regs[r0]) {
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@ -17,8 +17,6 @@
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_eqv_i32 1
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#define TCG_TARGET_HAS_nand_i32 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 1
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