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qtest/xive: Add group-interrupt test
Add XIVE2 tests for group interrupts and group interrupts that have been backlogged. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Frederic Barrat
Nicholas Piggin
parent
26c55b9941
commit
c2b7fade9f
1 changed files with 160 additions and 0 deletions
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@ -2,6 +2,8 @@
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* QTest testcase for PowerNV 10 interrupt controller (xive2)
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* - Test irq to hardware thread
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* - Test 'Pull Thread Context to Odd Thread Reporting Line'
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* - Test irq to hardware group
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* - Test irq to hardware group going through backlog
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*
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* Copyright (c) 2024, IBM Corporation.
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*
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@ -315,6 +317,158 @@ static void test_pull_thread_ctx_to_odd_thread_cl(QTestState *qts)
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word2 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD2);
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g_assert_cmphex(xive_get_field32(TM_QW3W2_VT, word2), ==, 0);
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}
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static void test_hw_group_irq(QTestState *qts)
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{
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uint32_t irq = 100;
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uint32_t irq_data = 0xdeadbeef;
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uint32_t end_index = 23;
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uint32_t chosen_one;
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uint32_t target_nvp = 0x81; /* group size = 4 */
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uint8_t priority = 6;
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uint32_t reg32;
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uint16_t reg16;
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uint8_t pq, nsr, cppr;
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printf("# ============================================================\n");
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printf("# Testing irq %d to hardware group of size 4\n", irq);
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/* irq config */
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set_eas(qts, irq, end_index, irq_data);
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set_end(qts, end_index, target_nvp, priority, true /* group */);
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/* enable and trigger irq */
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get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
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set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0);
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/* check irq is raised on cpu */
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pq = get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
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g_assert_cmpuint(pq, ==, XIVE_ESB_PENDING);
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/* find the targeted vCPU */
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for (chosen_one = 0; chosen_one < SMT; chosen_one++) {
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reg32 = get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
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nsr = reg32 >> 24;
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if (nsr == 0x82) {
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break;
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}
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}
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g_assert_cmphex(chosen_one, <, SMT);
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cppr = (reg32 >> 16) & 0xFF;
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g_assert_cmphex(nsr, ==, 0x82);
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g_assert_cmphex(cppr, ==, 0xFF);
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/* ack the irq */
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reg16 = get_tima16(qts, chosen_one, TM_SPC_ACK_HV_REG);
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nsr = reg16 >> 8;
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cppr = reg16 & 0xFF;
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g_assert_cmphex(nsr, ==, 0x82);
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g_assert_cmphex(cppr, ==, priority);
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/* check irq data is what was configured */
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reg32 = qtest_readl(qts, xive_get_queue_addr(end_index));
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g_assert_cmphex((reg32 & 0x7fffffff), ==, (irq_data & 0x7fffffff));
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/* End Of Interrupt */
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set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0);
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pq = get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
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g_assert_cmpuint(pq, ==, XIVE_ESB_RESET);
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/* reset CPPR */
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set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, 0xFF);
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reg32 = get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
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nsr = reg32 >> 24;
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cppr = (reg32 >> 16) & 0xFF;
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g_assert_cmphex(nsr, ==, 0x00);
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g_assert_cmphex(cppr, ==, 0xFF);
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}
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static void test_hw_group_irq_backlog(QTestState *qts)
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{
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uint32_t irq = 31;
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uint32_t irq_data = 0x01234567;
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uint32_t end_index = 129;
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uint32_t target_nvp = 0x81; /* group size = 4 */
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uint32_t chosen_one = 3;
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uint8_t blocking_priority, priority = 3;
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uint32_t reg32;
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uint16_t reg16;
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uint8_t pq, nsr, cppr, lsmfb, i;
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printf("# ============================================================\n");
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printf("# Testing irq %d to hardware group of size 4 going through " \
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"backlog\n",
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irq);
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/*
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* set current priority of all threads in the group to something
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* higher than what we're about to trigger
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*/
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blocking_priority = priority - 1;
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for (i = 0; i < SMT; i++) {
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set_tima8(qts, i, TM_QW3_HV_PHYS + TM_CPPR, blocking_priority);
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}
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/* irq config */
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set_eas(qts, irq, end_index, irq_data);
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set_end(qts, end_index, target_nvp, priority, true /* group */);
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/* enable and trigger irq */
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get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
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set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0);
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/* check irq is raised on cpu */
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pq = get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
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g_assert_cmpuint(pq, ==, XIVE_ESB_PENDING);
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/* check no interrupt is pending on the 2 possible targets */
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for (i = 0; i < SMT; i++) {
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reg32 = get_tima32(qts, i, TM_QW3_HV_PHYS + TM_WORD0);
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nsr = reg32 >> 24;
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cppr = (reg32 >> 16) & 0xFF;
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lsmfb = reg32 & 0xFF;
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g_assert_cmphex(nsr, ==, 0x0);
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g_assert_cmphex(cppr, ==, blocking_priority);
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g_assert_cmphex(lsmfb, ==, priority);
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}
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/* lower priority of one thread */
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set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, priority + 1);
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/* check backlogged interrupt is presented */
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reg32 = get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
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nsr = reg32 >> 24;
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cppr = (reg32 >> 16) & 0xFF;
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g_assert_cmphex(nsr, ==, 0x82);
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g_assert_cmphex(cppr, ==, priority + 1);
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/* ack the irq */
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reg16 = get_tima16(qts, chosen_one, TM_SPC_ACK_HV_REG);
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nsr = reg16 >> 8;
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cppr = reg16 & 0xFF;
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g_assert_cmphex(nsr, ==, 0x82);
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g_assert_cmphex(cppr, ==, priority);
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/* check irq data is what was configured */
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reg32 = qtest_readl(qts, xive_get_queue_addr(end_index));
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g_assert_cmphex((reg32 & 0x7fffffff), ==, (irq_data & 0x7fffffff));
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/* End Of Interrupt */
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set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0);
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pq = get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
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g_assert_cmpuint(pq, ==, XIVE_ESB_RESET);
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/* reset CPPR */
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set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, 0xFF);
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reg32 = get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
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nsr = reg32 >> 24;
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cppr = (reg32 >> 16) & 0xFF;
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lsmfb = reg32 & 0xFF;
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g_assert_cmphex(nsr, ==, 0x00);
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g_assert_cmphex(cppr, ==, 0xFF);
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g_assert_cmphex(lsmfb, ==, 0xFF);
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}
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static void test_xive(void)
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{
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QTestState *qts;
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@ -330,6 +484,12 @@ static void test_xive(void)
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/* omit reset_state here and use settings from test_hw_irq */
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test_pull_thread_ctx_to_odd_thread_cl(qts);
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reset_state(qts);
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test_hw_group_irq(qts);
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reset_state(qts);
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test_hw_group_irq_backlog(qts);
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reset_state(qts);
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test_flush_sync_inject(qts);
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