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Hexagon (target/hexagon) Improve code gen for predicated HVX instructions

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The following improvements are made for predicated HVX instructions
    During gen_commit_hvx, unconditionally move the "new" value into
        the dest
    Don't set slot_cancelled
    Remove runtime bookkeeping of which registers were updated
    Reduce the cases where gen_log_vreg_write[_pair] is called
        It's only needed for special operands VxxV and VyV
    Remove gen_log_qreg_write

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-15-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2023-03-06 18:58:28 -08:00
parent 7b84fd04bd
commit c2b33d0be9
8 changed files with 34 additions and 168 deletions
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3
target/hexagon/gen_analyze_funcs.py
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@ -110,8 +110,7 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
if (regid in {"d", "e", "x"}):
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(" ctx_log_qreg_write(ctx, %s, %s);\n" % \
(regN, predicated))
f.write(" ctx_log_qreg_write(ctx, %s);\n" % (regN))
elif (regid in {"s", "t", "u", "v"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))