mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-26 11:32:23 -06:00
hw/ide/piix: properly initialize the BMIBA register
According to the 82371FB documentation (82371FB.pdf, 2.3.9. BMIBA-BUS MASTER INTERFACE BASE ADDRESS REGISTER, April 1997), the register is 32bit wide. To properly reset it to default values, all 32bit need to be cleared. Bit #0 "Resource Type Indicator (RTE)" needs to be enabled. The initial change wrote just the lower 8 bit, leaving parts of the "Bus Master Interface Base Address" address at bit 15:4 unchanged. Fixes:e6a71ae327
("Add support for 82371FB (Step A1) and Improved support for 82371SB (Function 1)") Signed-off-by: Olaf Hering <olaf@aepfle.de> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230712074721.14728-1-olaf@aepfle.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> (cherry picked from commit230dfd9257
) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
parent
520d5fb4cb
commit
c280ac3b60
1 changed files with 1 additions and 1 deletions
|
@ -118,7 +118,7 @@ static void piix_ide_reset(DeviceState *dev)
|
|||
pci_set_word(pci_conf + PCI_COMMAND, 0x0000);
|
||||
pci_set_word(pci_conf + PCI_STATUS,
|
||||
PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
|
||||
pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */
|
||||
pci_set_long(pci_conf + 0x20, 0x1); /* BMIBA: 20-23h */
|
||||
}
|
||||
|
||||
static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp)
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue