motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-05 00:33:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/intc/loongarch_pch: Set version information at initial stage

Browse source 
Register PCH_PIC_INT_ID constains version and supported irq number
information, and it is read only register. The detailed value can
be set at initial stage, rather than read callback.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-5-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Bibo Mao 2025-05-07 10:31:36 +08:00 • committed by Song Gao
parent e95e4e818b
commit c2658b0de5
3 changed files with 30 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

13
hw/intc/loongarch_pic_common.c
View file

@ -49,6 +49,19 @@ static void loongarch_pic_common_reset_hold(Object *obj, ResetType type)
LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(obj);
int i;
/*
* With Loongson 7A1000 user manual
* Chapter 5.2 "Description of Interrupt-related Registers"
*
* Interrupt controller identification register 1
* Bit 24-31 Interrupt Controller ID
* Interrupt controller identification register 2
* Bit 0-7 Interrupt Controller version number
* Bit 16-23 The number of interrupt sources supported
*/
s->id.desc.id = PCH_PIC_INT_ID_VAL;
s->id.desc.version = PCH_PIC_INT_ID_VER;
s->id.desc.irq_num = s->irq_num - 1;
s->int_mask = UINT64_MAX;
s->htmsi_en = 0x0;
s->intedge = 0x0;