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Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Something
like this _must_ be presented on the list first so people can provide input
and cope with it.
This reverts commit 99a0949b72.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori
parent
99a0949b72
commit
c227f0995e
316 changed files with 3332 additions and 3325 deletions
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@ -70,8 +70,8 @@
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/*****************************************************************************/
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/* MMU model */
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typedef enum powerpc_mmu e_powerpc_mmu;
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enum powerpc_mmu {
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typedef enum powerpc_mmu_t powerpc_mmu_t;
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enum powerpc_mmu_t {
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POWERPC_MMU_UNKNOWN = 0x00000000,
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/* Standard 32 bits PowerPC MMU */
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POWERPC_MMU_32B = 0x00000001,
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@ -104,8 +104,8 @@ enum powerpc_mmu {
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/*****************************************************************************/
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/* Exception model */
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typedef enum powerpc_excp e_powerpc_excp;
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enum powerpc_excp {
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typedef enum powerpc_excp_t powerpc_excp_t;
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enum powerpc_excp_t {
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POWERPC_EXCP_UNKNOWN = 0,
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/* Standard PowerPC exception model */
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POWERPC_EXCP_STD,
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@ -258,8 +258,8 @@ enum {
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/*****************************************************************************/
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/* Input pins model */
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typedef enum powerpc_input e_powerpc_input;
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enum powerpc_input {
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typedef enum powerpc_input_t powerpc_input_t;
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enum powerpc_input_t {
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PPC_FLAGS_INPUT_UNKNOWN = 0,
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/* PowerPC 6xx bus */
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PPC_FLAGS_INPUT_6xx,
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@ -278,18 +278,20 @@ enum powerpc_input {
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#define PPC_INPUT(env) (env->bus_model)
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/*****************************************************************************/
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typedef struct ppc_def a_ppc_def;
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typedef struct opc_handler an_opc_handler;
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typedef struct ppc_def_t ppc_def_t;
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typedef struct opc_handler_t opc_handler_t;
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/*****************************************************************************/
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/* Types used to describe some PowerPC registers */
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typedef struct CPUPPCState CPUPPCState;
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typedef struct ppc_tb a_ppc_tb;
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typedef struct ppc_spr a_ppc_spr;
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typedef struct ppc_dcr a_ppc_dcr;
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typedef struct ppc_tb_t ppc_tb_t;
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typedef struct ppc_spr_t ppc_spr_t;
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typedef struct ppc_dcr_t ppc_dcr_t;
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typedef union ppc_avr_t ppc_avr_t;
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typedef union ppc_tlb_t ppc_tlb_t;
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/* SPR access micro-ops generations callbacks */
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struct ppc_spr {
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struct ppc_spr_t {
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void (*uea_read)(void *opaque, int gpr_num, int spr_num);
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void (*uea_write)(void *opaque, int spr_num, int gpr_num);
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#if !defined(CONFIG_USER_ONLY)
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@ -302,7 +304,7 @@ struct ppc_spr {
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};
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/* Altivec registers (128 bits) */
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union ppc_avr {
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union ppc_avr_t {
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float32 f[4];
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uint8_t u8[16];
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uint16_t u16[8];
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@ -314,16 +316,16 @@ union ppc_avr {
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};
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/* Software TLB cache */
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typedef struct ppc6xx_tlb a_ppc6xx_tlb;
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struct ppc6xx_tlb {
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typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
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struct ppc6xx_tlb_t {
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target_ulong pte0;
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target_ulong pte1;
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target_ulong EPN;
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};
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typedef struct ppcemb_tlb a_ppcemb_tlb;
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struct ppcemb_tlb {
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a_target_phys_addr RPN;
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typedef struct ppcemb_tlb_t ppcemb_tlb_t;
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struct ppcemb_tlb_t {
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target_phys_addr_t RPN;
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target_ulong EPN;
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target_ulong PID;
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target_ulong size;
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@ -331,13 +333,13 @@ struct ppcemb_tlb {
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uint32_t attr; /* Storage attributes */
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};
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union ppc_tlb {
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a_ppc6xx_tlb tlb6;
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a_ppcemb_tlb tlbe;
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union ppc_tlb_t {
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ppc6xx_tlb_t tlb6;
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ppcemb_tlb_t tlbe;
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};
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typedef struct ppc_slb a_ppc_slb;
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struct ppc_slb {
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typedef struct ppc_slb_t ppc_slb_t;
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struct ppc_slb_t {
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uint64_t tmp64;
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uint32_t tmp;
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};
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@ -588,7 +590,7 @@ struct CPUPPCState {
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/* Address space register */
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target_ulong asr;
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/* PowerPC 64 SLB area */
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a_ppc_slb slb[64];
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ppc_slb_t slb[64];
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int slb_nr;
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#endif
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/* segment registers */
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@ -605,7 +607,7 @@ struct CPUPPCState {
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int last_way; /* Last used way used to allocate TLB in a LRU way */
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int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
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int nb_pids; /* Number of available PID registers */
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union ppc_tlb *tlb; /* TLB is optional. Allocate them only if needed */
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ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
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/* 403 dedicated access protection registers */
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target_ulong pb[4];
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#endif
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@ -613,9 +615,9 @@ struct CPUPPCState {
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/* Other registers */
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/* Special purpose registers */
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target_ulong spr[1024];
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a_ppc_spr spr_cb[1024];
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ppc_spr_t spr_cb[1024];
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/* Altivec registers */
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union ppc_avr avr[32];
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ppc_avr_t avr[32];
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uint32_t vscr;
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/* SPE registers */
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uint64_t spe_acc;
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@ -626,9 +628,9 @@ struct CPUPPCState {
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/* Internal devices resources */
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/* Time base and decrementer */
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a_ppc_tb *tb_env;
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ppc_tb_t *tb_env;
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/* Device control registers */
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a_ppc_dcr *dcr_env;
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ppc_dcr_t *dcr_env;
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int dcache_line_size;
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int icache_line_size;
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@ -636,9 +638,9 @@ struct CPUPPCState {
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/* Those resources are used during exception processing */
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/* CPU model definition */
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target_ulong msr_mask;
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e_powerpc_mmu mmu_model;
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e_powerpc_excp excp_model;
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e_powerpc_input bus_model;
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powerpc_mmu_t mmu_model;
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powerpc_excp_t excp_model;
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powerpc_input_t bus_model;
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int bfd_mach;
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uint32_t flags;
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uint64_t insns_flags;
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@ -665,7 +667,7 @@ struct CPUPPCState {
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target_ulong nip;
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/* opcode handlers */
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an_opc_handler *opcodes[0x40];
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opc_handler_t *opcodes[0x40];
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/* Those resources are used only in Qemu core */
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target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
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@ -681,12 +683,12 @@ struct CPUPPCState {
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};
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/* Context used internally during MMU translations */
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typedef struct mmu_ctx a_mmu_ctx;
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struct mmu_ctx {
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a_target_phys_addr raddr; /* Real address */
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a_target_phys_addr eaddr; /* Effective address */
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typedef struct mmu_ctx_t mmu_ctx_t;
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struct mmu_ctx_t {
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target_phys_addr_t raddr; /* Real address */
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target_phys_addr_t eaddr; /* Effective address */
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int prot; /* Protection bits */
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a_target_phys_addr pg_addr[2]; /* PTE tables base addresses */
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target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
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target_ulong ptem; /* Virtual segment ID | API */
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int key; /* Access key */
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int nx; /* Non-execute area */
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@ -705,7 +707,7 @@ int cpu_ppc_signal_handler (int host_signum, void *pinfo,
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int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu);
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#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
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int get_physical_address (CPUPPCState *env, a_mmu_ctx *ctx, target_ulong vaddr,
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int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
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int rw, int access_type);
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void do_interrupt (CPUPPCState *env);
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void ppc_hw_interrupt (CPUPPCState *env);
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@ -736,8 +738,8 @@ void cpu_ppc_reset (void *opaque);
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void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
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const a_ppc_def *cpu_ppc_find_by_name (const char *name);
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int cpu_ppc_register_internal (CPUPPCState *env, const a_ppc_def *def);
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const ppc_def_t *cpu_ppc_find_by_name (const char *name);
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int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
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/* Time-base and decrementer management */
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#ifndef NO_CPU_IO_DEFS
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@ -795,8 +797,8 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
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}
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/* Device control registers */
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int ppc_dcr_read (a_ppc_dcr *dcr_env, int dcrn, target_ulong *valp);
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int ppc_dcr_write (a_ppc_dcr *dcr_env, int dcrn, target_ulong val);
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int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
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int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
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#define cpu_init cpu_ppc_init
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#define cpu_exec cpu_ppc_exec
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