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https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 16:23:55 -06:00
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Something
like this _must_ be presented on the list first so people can provide input
and cope with it.
This reverts commit 99a0949b72.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori
parent
99a0949b72
commit
c227f0995e
316 changed files with 3332 additions and 3325 deletions
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@ -41,7 +41,7 @@
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/*****************************************************************************/
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/* Generic PowerPC 4xx processor instanciation */
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CPUState *ppc4xx_init (const char *cpu_model,
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a_clk_setup *cpu_clk, a_clk_setup *tb_clk,
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clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
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uint32_t sysclk)
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{
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CPUState *env;
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@ -81,8 +81,8 @@ enum {
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};
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#define UIC_MAX_IRQ 32
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typedef struct ppcuic a_ppcuic;
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struct ppcuic {
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typedef struct ppcuic_t ppcuic_t;
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struct ppcuic_t {
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uint32_t dcr_base;
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int use_vectors;
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uint32_t level; /* Remembers the state of level-triggered interrupts. */
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@ -96,7 +96,7 @@ struct ppcuic {
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qemu_irq *irqs;
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};
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static void ppcuic_trigger_irq (a_ppcuic *uic)
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static void ppcuic_trigger_irq (ppcuic_t *uic)
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{
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uint32_t ir, cr;
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int start, end, inc, i;
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@ -149,7 +149,7 @@ static void ppcuic_trigger_irq (a_ppcuic *uic)
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static void ppcuic_set_irq (void *opaque, int irq_num, int level)
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{
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a_ppcuic *uic;
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ppcuic_t *uic;
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uint32_t mask, sr;
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uic = opaque;
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@ -185,7 +185,7 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
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static target_ulong dcr_read_uic (void *opaque, int dcrn)
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{
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a_ppcuic *uic;
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ppcuic_t *uic;
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target_ulong ret;
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uic = opaque;
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@ -231,7 +231,7 @@ static target_ulong dcr_read_uic (void *opaque, int dcrn)
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static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
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{
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a_ppcuic *uic;
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ppcuic_t *uic;
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uic = opaque;
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dcrn -= uic->dcr_base;
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@ -274,7 +274,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
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static void ppcuic_reset (void *opaque)
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{
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a_ppcuic *uic;
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ppcuic_t *uic;
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uic = opaque;
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uic->uiccr = 0x00000000;
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@ -291,10 +291,10 @@ static void ppcuic_reset (void *opaque)
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qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
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uint32_t dcr_base, int has_ssr, int has_vr)
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{
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a_ppcuic *uic;
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ppcuic_t *uic;
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int i;
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uic = qemu_mallocz(sizeof(a_ppcuic));
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uic = qemu_mallocz(sizeof(ppcuic_t));
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uic->dcr_base = dcr_base;
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uic->irqs = irqs;
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if (has_vr)
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@ -311,12 +311,12 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
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/*****************************************************************************/
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/* SDRAM controller */
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typedef struct ppc4xx_sdram a_ppc4xx_sdram;
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struct ppc4xx_sdram {
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typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
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struct ppc4xx_sdram_t {
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uint32_t addr;
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int nbanks;
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a_target_phys_addr ram_bases[4];
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a_target_phys_addr ram_sizes[4];
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target_phys_addr_t ram_bases[4];
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target_phys_addr_t ram_sizes[4];
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uint32_t besr0;
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uint32_t besr1;
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uint32_t bear;
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@ -337,11 +337,11 @@ enum {
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};
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/* XXX: TOFIX: some patches have made this code become inconsistent:
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* there are type inconsistencies, mixing a_target_phys_addr, target_ulong
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* there are type inconsistencies, mixing target_phys_addr_t, target_ulong
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* and uint32_t
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*/
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static uint32_t sdram_bcr (a_target_phys_addr ram_base,
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a_target_phys_addr ram_size)
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static uint32_t sdram_bcr (target_phys_addr_t ram_base,
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target_phys_addr_t ram_size)
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{
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uint32_t bcr;
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@ -378,7 +378,7 @@ static uint32_t sdram_bcr (a_target_phys_addr ram_base,
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return bcr;
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}
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static inline a_target_phys_addr sdram_base(uint32_t bcr)
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static inline target_phys_addr_t sdram_base(uint32_t bcr)
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{
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return bcr & 0xFF800000;
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}
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@ -419,7 +419,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
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}
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}
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static void sdram_map_bcr (a_ppc4xx_sdram *sdram)
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static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
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{
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int i;
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@ -434,7 +434,7 @@ static void sdram_map_bcr (a_ppc4xx_sdram *sdram)
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}
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}
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static void sdram_unmap_bcr (a_ppc4xx_sdram *sdram)
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static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
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{
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int i;
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@ -451,7 +451,7 @@ static void sdram_unmap_bcr (a_ppc4xx_sdram *sdram)
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static target_ulong dcr_read_sdram (void *opaque, int dcrn)
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{
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a_ppc4xx_sdram *sdram;
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ppc4xx_sdram_t *sdram;
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target_ulong ret;
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sdram = opaque;
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@ -519,7 +519,7 @@ static target_ulong dcr_read_sdram (void *opaque, int dcrn)
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static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
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{
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a_ppc4xx_sdram *sdram;
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ppc4xx_sdram_t *sdram;
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sdram = opaque;
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switch (dcrn) {
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@ -604,7 +604,7 @@ static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
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static void sdram_reset (void *opaque)
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{
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a_ppc4xx_sdram *sdram;
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ppc4xx_sdram_t *sdram;
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sdram = opaque;
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sdram->addr = 0x00000000;
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@ -624,21 +624,21 @@ static void sdram_reset (void *opaque)
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}
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void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
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a_target_phys_addr *ram_bases,
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a_target_phys_addr *ram_sizes,
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target_phys_addr_t *ram_bases,
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target_phys_addr_t *ram_sizes,
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int do_init)
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{
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a_ppc4xx_sdram *sdram;
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ppc4xx_sdram_t *sdram;
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sdram = qemu_mallocz(sizeof(a_ppc4xx_sdram));
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sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
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sdram->irq = irq;
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sdram->nbanks = nbanks;
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memset(sdram->ram_bases, 0, 4 * sizeof(a_target_phys_addr));
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memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
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memcpy(sdram->ram_bases, ram_bases,
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nbanks * sizeof(a_target_phys_addr));
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memset(sdram->ram_sizes, 0, 4 * sizeof(a_target_phys_addr));
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nbanks * sizeof(target_phys_addr_t));
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memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
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memcpy(sdram->ram_sizes, ram_sizes,
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nbanks * sizeof(a_target_phys_addr));
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nbanks * sizeof(target_phys_addr_t));
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sdram_reset(sdram);
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qemu_register_reset(&sdram_reset, sdram);
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ppc_dcr_register(env, SDRAM0_CFGADDR,
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@ -656,12 +656,12 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
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* The 4xx SDRAM controller supports a small number of banks, and each bank
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* must be one of a small set of sizes. The number of banks and the supported
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* sizes varies by SoC. */
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a_ram_addr ppc4xx_sdram_adjust(a_ram_addr ram_size, int nr_banks,
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a_target_phys_addr ram_bases[],
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a_target_phys_addr ram_sizes[],
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ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
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target_phys_addr_t ram_bases[],
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target_phys_addr_t ram_sizes[],
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const unsigned int sdram_bank_sizes[])
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{
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a_ram_addr size_left = ram_size;
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ram_addr_t size_left = ram_size;
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int i;
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int j;
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