motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-03 07:43:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: vector mask-register logical instructions

Browse source 
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-50-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2020-07-01 23:25:37 +08:00 • committed by Alistair Francis
parent 696b0c260a
commit c21f34aebf
4 changed files with 92 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

40
target/riscv/vector_helper.c
View file

@ -4502,3 +4502,43 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
*((uint64_t *)vd) = s1;
clearq(vd, 1, sizeof(uint64_t), tot);
}
/*
*** Vector Mask Operations
*/
/* Vector Mask-Register Logical Instructions */
#define GEN_VEXT_MASK_VV(NAME, OP) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t mlen = vext_mlen(desc); \
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
\
for (i = 0; i < vl; i++) { \
a = vext_elem_mask(vs1, mlen, i); \
b = vext_elem_mask(vs2, mlen, i); \
vext_set_elem_mask(vd, mlen, i, OP(b, a)); \
} \
for (; i < vlmax; i++) { \
vext_set_elem_mask(vd, mlen, i, 0); \
} \
}
#define DO_NAND(N, M) (!(N & M))
#define DO_ANDNOT(N, M) (N & !M)
#define DO_NOR(N, M) (!(N | M))
#define DO_ORNOT(N, M) (N | !M)
#define DO_XNOR(N, M) (!(N ^ M))
GEN_VEXT_MASK_VV(vmand_mm, DO_AND)
GEN_VEXT_MASK_VV(vmnand_mm, DO_NAND)
GEN_VEXT_MASK_VV(vmandnot_mm, DO_ANDNOT)
GEN_VEXT_MASK_VV(vmxor_mm, DO_XOR)
GEN_VEXT_MASK_VV(vmor_mm, DO_OR)
GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR)
GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT)
GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR)