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target-arm queue:

Browse source 
* hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
  * hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
  * accel/tcg: Preserve PAGE_ANON when changing page permissions
  * target/arm: Check PAGE_WRITE_ORG for MTE writeability
  * exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmB0IXMZHHBldGVyLm1h
 eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3jXoD/9XnA+/RELoDZAuCw1h10At
 M7QhbMc1ySgxbq15a5lTMNyE/FDd4sGoDkmK/VI0kxYlsoYyXmirFkQUG31p/ypp
 +Md0JnA5YTo32zB1wfzkors+dkKpTMq97QvboQGlsjdu3fz5t7eARzwq9jyM+iG/
 eieN/mdQU/X82TPc+v7zr3EVbmeXl2ocAVWBuvQ7HBftqIbqiAa/pEErCfbuZ33r
 F0j6AsXQUT/b8CH3jNRBtQTdG1wXBbhh+gxViR0kLS3WZMPT3vwemlYPWTE291b1
 k8ha08Bfvq6Qf3KqxozLxtJjqLedIq3qEfZl24Qtg0vtBsP/aggOhxfBJspaYQzn
 ZgfC8+25mZVDAItgg3cwcLjgzZ+Aq+4zrgvNJ+jjMN5TBhQXwTzNzBc54Uik2JEh
 /sFs9aMqDiSJrZYM1DF5DDfnI5TGILZQA9L8bgvqoLXehHrdbPPptBH5+s7DsDnw
 O+4P7Pikv17dHwAnT2k4cjsiZ+oCV1xJjVjPBQ1i7Iyl2T24cMtTywazdGNefG6V
 q/C62/8ml92PmEWadIk1i2QEyjiqNifXO2zYUicPwI2WAIK3urVIbTVwInbmNiCT
 +BeqmZyBlWxr3BZgLexoA/asGUOffe3iRzuQojfCAIv8lqZAqrATAf1Qrw1+sx9S
 Cye0AIOZokOIusHxie/BGA==
 =T96G
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210412' into staging

target-arm queue:
 * hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
 * hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
 * accel/tcg: Preserve PAGE_ANON when changing page permissions
 * target/arm: Check PAGE_WRITE_ORG for MTE writeability
 * exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1

# gpg: Signature made Mon 12 Apr 2021 11:31:15 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210412:
  exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
  target/arm: Check PAGE_WRITE_ORG for MTE writeability
  accel/tcg: Preserve PAGE_ANON when changing page permissions
  hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
  hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-04-12 12:12:09 +01:00
commit c1e90def01
8 changed files with 66 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

12
hw/arm/smmuv3.c
View file

@ -980,16 +980,20 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
}
case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */
{
uint32_t start = CMD_SID(&cmd);
uint32_t sid = CMD_SID(&cmd), mask;
uint8_t range = CMD_STE_RANGE(&cmd);
uint64_t end = start + (1ULL << (range + 1)) - 1;
SMMUSIDRange sid_range = {start, end};
SMMUSIDRange sid_range;
if (CMD_SSEC(&cmd)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
trace_smmuv3_cmdq_cfgi_ste_range(start, end);
mask = (1ULL << (range + 1)) - 1;
sid_range.start = sid & ~mask;
sid_range.end = sid_range.start + mask;
trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end);
g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
&sid_range);
break;

4
hw/arm/virt-acpi-build.c
View file

@ -292,8 +292,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
smmu->event_gsiv = cpu_to_le32(irq);
smmu->pri_gsiv = cpu_to_le32(irq + 1);
smmu->gerr_gsiv = cpu_to_le32(irq + 2);
smmu->sync_gsiv = cpu_to_le32(irq + 3);
smmu->sync_gsiv = cpu_to_le32(irq + 2);
smmu->gerr_gsiv = cpu_to_le32(irq + 3);
/* Identity RID mapping covering the whole input RID range */
idmap = &smmu->id_mapping_array[0];