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hw: move PCI bridges to hw/pci-* or hw/ARCH
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
8ac5c6510b
commit
c0907c9e64
35 changed files with 26 additions and 27 deletions
217
hw/pci-bridge/xio3130_downstream.c
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217
hw/pci-bridge/xio3130_downstream.c
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@ -0,0 +1,217 @@
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/*
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* x3130_downstream.c
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* TI X3130 pci express downstream port switch
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/pci/pci_ids.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/pcie.h"
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#include "hw/xio3130_downstream.h"
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#define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */
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#define XIO3130_REVISION 0x1
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#define XIO3130_MSI_OFFSET 0x70
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#define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
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#define XIO3130_MSI_NR_VECTOR 1
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#define XIO3130_SSVID_OFFSET 0x80
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#define XIO3130_SSVID_SVID 0
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#define XIO3130_SSVID_SSID 0
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#define XIO3130_EXP_OFFSET 0x90
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#define XIO3130_AER_OFFSET 0x100
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static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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pci_bridge_write_config(d, address, val, len);
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pcie_cap_flr_write_config(d, address, val, len);
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pcie_cap_slot_write_config(d, address, val, len);
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pcie_aer_write_config(d, address, val, len);
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}
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static void xio3130_downstream_reset(DeviceState *qdev)
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{
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PCIDevice *d = PCI_DEVICE(qdev);
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pcie_cap_deverr_reset(d);
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pcie_cap_slot_reset(d);
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pcie_cap_ari_reset(d);
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pci_bridge_reset(qdev);
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}
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static int xio3130_downstream_initfn(PCIDevice *d)
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{
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PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
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PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
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PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
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int rc;
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rc = pci_bridge_initfn(d, TYPE_PCIE_BUS);
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if (rc < 0) {
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return rc;
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}
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pcie_port_init_reg(d);
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rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
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XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
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XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
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if (rc < 0) {
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goto err_bridge;
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}
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rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
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XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
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if (rc < 0) {
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goto err_bridge;
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}
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rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
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p->port);
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if (rc < 0) {
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goto err_msi;
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}
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pcie_cap_flr_init(d);
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pcie_cap_deverr_init(d);
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pcie_cap_slot_init(d, s->slot);
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pcie_chassis_create(s->chassis);
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rc = pcie_chassis_add_slot(s);
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if (rc < 0) {
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goto err_pcie_cap;
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}
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pcie_cap_ari_init(d);
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rc = pcie_aer_init(d, XIO3130_AER_OFFSET);
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if (rc < 0) {
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goto err;
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}
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return 0;
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err:
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pcie_chassis_del_slot(s);
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err_pcie_cap:
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pcie_cap_exit(d);
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err_msi:
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msi_uninit(d);
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err_bridge:
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pci_bridge_exitfn(d);
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return rc;
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}
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static void xio3130_downstream_exitfn(PCIDevice *d)
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{
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PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
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PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
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PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
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pcie_aer_exit(d);
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pcie_chassis_del_slot(s);
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pcie_cap_exit(d);
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msi_uninit(d);
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pci_bridge_exitfn(d);
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}
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PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
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const char *bus_name, pci_map_irq_fn map_irq,
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uint8_t port, uint8_t chassis,
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uint16_t slot)
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{
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PCIDevice *d;
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PCIBridge *br;
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DeviceState *qdev;
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d = pci_create_multifunction(bus, devfn, multifunction,
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"xio3130-downstream");
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if (!d) {
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return NULL;
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}
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br = DO_UPCAST(PCIBridge, dev, d);
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qdev = &br->dev.qdev;
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pci_bridge_map_irq(br, bus_name, map_irq);
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qdev_prop_set_uint8(qdev, "port", port);
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qdev_prop_set_uint8(qdev, "chassis", chassis);
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qdev_prop_set_uint16(qdev, "slot", slot);
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qdev_init_nofail(qdev);
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return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
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}
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static const VMStateDescription vmstate_xio3130_downstream = {
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.name = "xio3130-express-downstream-port",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = pcie_cap_slot_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
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VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
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vmstate_pcie_aer_log, PCIEAERLog),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property xio3130_downstream_properties[] = {
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DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
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DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
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DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
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DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
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port.br.dev.exp.aer_log.log_max,
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PCIE_AER_LOG_MAX_DEFAULT),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->is_express = 1;
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k->is_bridge = 1;
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k->config_write = xio3130_downstream_write_config;
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k->init = xio3130_downstream_initfn;
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k->exit = xio3130_downstream_exitfn;
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k->vendor_id = PCI_VENDOR_ID_TI;
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k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
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k->revision = XIO3130_REVISION;
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dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
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dc->reset = xio3130_downstream_reset;
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dc->vmsd = &vmstate_xio3130_downstream;
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dc->props = xio3130_downstream_properties;
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}
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static const TypeInfo xio3130_downstream_info = {
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.name = "xio3130-downstream",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIESlot),
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.class_init = xio3130_downstream_class_init,
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};
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static void xio3130_downstream_register_types(void)
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{
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type_register_static(&xio3130_downstream_info);
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}
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type_init(xio3130_downstream_register_types)
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/*
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* Local variables:
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* c-indent-level: 4
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* c-basic-offset: 4
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* tab-width: 8
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* indent-tab-mode: nil
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* End:
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*/
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