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hw/block:m25p80: Fix coding style

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Fix coding style issues from checkpatch.pl

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2024-10-22 17:40:54 +08:00 • committed by Cédric Le Goater
parent 05d501a1ea
commit c0400e3ac6
1 changed files with 14 additions and 8 deletions
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22
hw/block/m25p80.c
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@ -61,7 +61,8 @@ typedef struct FlashPartInfo {
*/ */
uint8_t id[SPI_NOR_MAX_ID_LEN]; uint8_t id[SPI_NOR_MAX_ID_LEN];
uint8_t id_len; uint8_t id_len;
/* there is confusion between manufacturers as to what a sector is. In this /*
* there is confusion between manufacturers as to what a sector is. In this
* device model, a "sector" is the size that is erased by the ERASE_SECTOR * device model, a "sector" is the size that is erased by the ERASE_SECTOR
* command (opcode 0xd8). * command (opcode 0xd8).
*/ */
@ -168,7 +169,7 @@ typedef struct FlashPartInfo {
/* /*
* Spansion read mode command length in bytes, * Spansion read mode command length in bytes,
* the mode is currently not supported. * the mode is currently not supported.
*/ */
#define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
#define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
@ -189,7 +190,8 @@ static const FlashPartInfo known_devices[] = {
{ INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
/* Atmel EEPROMS - it is assumed, that don't care bit in command /*
* Atmel EEPROMS - it is assumed, that don't care bit in command
* is set to 0. Block protection is not supported. * is set to 0. Block protection is not supported.
*/ */
{ INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
@ -275,10 +277,13 @@ static const FlashPartInfo known_devices[] = {
{ INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
{ INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
{ INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
{ INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096,
{ INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, ER_4K | ER_32K, 2) },
{ INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096,
ER_4K | ER_32K, 2) },
/* Spansion -- single (large) sector size only, at least /*
* Spansion -- single (large) sector size only, at least
* for the chips listed here (without boot sectors). * for the chips listed here (without boot sectors).
*/ */
{ INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
@ -549,7 +554,8 @@ static void blk_sync_complete(void *opaque, int ret)
qemu_iovec_destroy(iov); qemu_iovec_destroy(iov);
g_free(iov); g_free(iov);
/* do nothing. Masters do not directly interact with the backing store, /*
* do nothing. Masters do not directly interact with the backing store,
* only the working copy so no mutexing required. * only the working copy so no mutexing required.
*/ */
} }
@ -1843,7 +1849,7 @@ static void m25p80_register_types(void)
type_register_static(&m25p80_info); type_register_static(&m25p80_info);
for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
TypeInfo ti = { const TypeInfo ti = {
.name = known_devices[i].part_name, .name = known_devices[i].part_name,
.parent = TYPE_M25P80, .parent = TYPE_M25P80,
.class_init = m25p80_class_init, .class_init = m25p80_class_init,