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tcg: Merge INDEX_op_muls2_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
5641afdf9b
commit
bfe964809b
7 changed files with 21 additions and 27 deletions
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@ -604,7 +604,7 @@ Multiword arithmetic support
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- | Similar to mul, except two unsigned inputs *t1* and *t2* yielding the full
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double-word product *t0*. The latter is returned in two single-word outputs.
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* - muls2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2*
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* - muls2 *t0_low*, *t0_high*, *t1*, *t2*
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- | Similar to mulu2, except the two inputs *t1* and *t2* are signed.
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@ -51,6 +51,7 @@ DEF(divu, 1, 2, 0, TCG_OPF_INT)
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DEF(divu2, 2, 3, 0, TCG_OPF_INT)
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DEF(eqv, 1, 2, 0, TCG_OPF_INT)
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DEF(mul, 1, 2, 0, TCG_OPF_INT)
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DEF(muls2, 2, 2, 0, TCG_OPF_INT)
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DEF(mulsh, 1, 2, 0, TCG_OPF_INT)
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DEF(muluh, 1, 2, 0, TCG_OPF_INT)
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DEF(nand, 1, 2, 0, TCG_OPF_INT)
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@ -92,7 +93,6 @@ DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
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DEF(add2_i32, 2, 4, 0, 0)
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DEF(sub2_i32, 2, 4, 0, 0)
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DEF(mulu2_i32, 2, 2, 0, 0)
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DEF(muls2_i32, 2, 2, 0, 0)
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DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
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DEF(setcond2_i32, 1, 4, 1, 0)
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@ -134,7 +134,6 @@ DEF(bswap64_i64, 1, 1, 1, 0)
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DEF(add2_i64, 2, 4, 0, 0)
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DEF(sub2_i64, 2, 4, 0, 0)
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DEF(mulu2_i64, 2, 2, 0, 0)
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DEF(muls2_i64, 2, 2, 0, 0)
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#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
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@ -2074,16 +2074,17 @@ static bool fold_multiply2(OptContext *ctx, TCGOp *op)
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h = (int32_t)(l >> 32);
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l = (int32_t)l;
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break;
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case INDEX_op_muls2_i32:
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l = (int64_t)(int32_t)a * (int32_t)b;
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h = l >> 32;
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l = (int32_t)l;
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break;
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case INDEX_op_mulu2_i64:
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mulu64(&l, &h, a, b);
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break;
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case INDEX_op_muls2_i64:
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muls64(&l, &h, a, b);
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case INDEX_op_muls2:
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if (ctx->type == TCG_TYPE_I32) {
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l = (int64_t)(int32_t)a * (int32_t)b;
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h = l >> 32;
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l = (int32_t)l;
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} else {
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muls64(&l, &h, a, b);
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}
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break;
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default:
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g_assert_not_reached();
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@ -2973,7 +2974,7 @@ void tcg_optimize(TCGContext *s)
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case INDEX_op_muluh:
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done = fold_mul_highpart(&ctx, op);
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break;
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CASE_OP_32_64(muls2):
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case INDEX_op_muls2:
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CASE_OP_32_64(mulu2):
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done = fold_multiply2(&ctx, op);
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break;
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@ -1162,8 +1162,8 @@ void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2)
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void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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if (tcg_op_supported(INDEX_op_muls2_i32, TCG_TYPE_I32, 0)) {
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tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2);
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if (tcg_op_supported(INDEX_op_muls2, TCG_TYPE_I32, 0)) {
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tcg_gen_op4_i32(INDEX_op_muls2, rl, rh, arg1, arg2);
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} else if (tcg_op_supported(INDEX_op_mulsh, TCG_TYPE_I32, 0)) {
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TCGv_i32 t = tcg_temp_ebb_new_i32();
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tcg_gen_op3_i32(INDEX_op_mul, t, arg1, arg2);
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@ -2880,8 +2880,8 @@ void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
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void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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if (tcg_op_supported(INDEX_op_muls2_i64, TCG_TYPE_I64, 0)) {
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tcg_gen_op4_i64(INDEX_op_muls2_i64, rl, rh, arg1, arg2);
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if (tcg_op_supported(INDEX_op_muls2, TCG_TYPE_I64, 0)) {
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tcg_gen_op4_i64(INDEX_op_muls2, rl, rh, arg1, arg2);
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} else if (tcg_op_supported(INDEX_op_mulsh, TCG_TYPE_I64, 0)) {
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TCGv_i64 t = tcg_temp_ebb_new_i64();
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tcg_gen_op3_i64(INDEX_op_mul, t, arg1, arg2);
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@ -1041,8 +1041,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
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OUTOP(INDEX_op_divu2, TCGOutOpDivRem, outop_divu2),
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OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
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OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
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OUTOP(INDEX_op_muls2_i32, TCGOutOpMul2, outop_muls2),
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OUTOP(INDEX_op_muls2_i64, TCGOutOpMul2, outop_muls2),
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OUTOP(INDEX_op_muls2, TCGOutOpMul2, outop_muls2),
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OUTOP(INDEX_op_mulsh, TCGOutOpBinary, outop_mulsh),
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OUTOP(INDEX_op_muluh, TCGOutOpBinary, outop_muluh),
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OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand),
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@ -4008,8 +4007,7 @@ liveness_pass_1(TCGContext *s)
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}
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goto do_not_remove;
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case INDEX_op_muls2_i32:
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case INDEX_op_muls2_i64:
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case INDEX_op_muls2:
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opc_new = INDEX_op_mul;
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opc_new2 = INDEX_op_mulsh;
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goto do_mul2;
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@ -5477,8 +5475,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
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}
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break;
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case INDEX_op_muls2_i32:
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case INDEX_op_muls2_i64:
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case INDEX_op_muls2:
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{
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const TCGOutOpMul2 *out =
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container_of(all_outop[op->opc], TCGOutOpMul2, base);
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@ -581,8 +581,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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tci_args_rr(insn, &r0, &r1);
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regs[r0] = ctpop_tr(regs[r1]);
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break;
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case INDEX_op_muls2_i32:
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case INDEX_op_muls2_i64:
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case INDEX_op_muls2:
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tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
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#if TCG_TARGET_REG_BITS == 32
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tmp64 = (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3];
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@ -1095,10 +1094,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
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str_r(r3), str_r(r4), str_c(c));
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break;
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case INDEX_op_muls2:
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case INDEX_op_mulu2_i32:
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case INDEX_op_mulu2_i64:
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case INDEX_op_muls2_i32:
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case INDEX_op_muls2_i64:
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tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
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info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
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op_name, str_r(r0), str_r(r1),
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@ -716,8 +716,7 @@ static TCGConstraintSetIndex cset_mul2(TCGType type, unsigned flags)
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static void tgen_muls2(TCGContext *s, TCGType type,
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TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3)
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{
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tcg_out_op_rrrr(s, glue(INDEX_op_muls2_i,TCG_TARGET_REG_BITS),
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a0, a1, a2, a3);
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tcg_out_op_rrrr(s, INDEX_op_muls2, a0, a1, a2, a3);
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}
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static const TCGOutOpMul2 outop_muls2 = {
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