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target/riscv: Fix target address to update badaddr

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Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc before misalign check, then update it into badaddr
and restore cpu_pc to current pc if exception is triggered.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-05-26 15:21:18 +08:00 • committed by Alistair Francis
parent 3bd87176ee
commit bfc4f9e351
3 changed files with 28 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

21
target/riscv/translate.c
View file

@ -224,21 +224,18 @@ static void decode_save_opc(DisasContext *ctx)
ctx->insn_start = NULL;
}
static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
target_ulong dest)
{
if (get_xl(ctx) == MXL_RV32) {
dest = (int32_t)dest;
}
tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_movi_tl(target, dest);
}
static void gen_set_pc(DisasContext *ctx, TCGv dest)
static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
{
if (get_xl(ctx) == MXL_RV32) {
tcg_gen_ext32s_tl(cpu_pc, dest);
} else {
tcg_gen_mov_tl(cpu_pc, dest);
}
gen_pc_plus_diff(cpu_pc, ctx, dest);
}
static void generate_exception(DisasContext *ctx, int excp)
@ -259,9 +256,9 @@ static void gen_exception_illegal(DisasContext *ctx)
}
}
static void gen_exception_inst_addr_mis(DisasContext *ctx)
static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target)
{
tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
tcg_gen_st_tl(target, cpu_env, offsetof(CPURISCVState, badaddr));
generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
}
@ -553,7 +550,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
next_pc = ctx->base.pc_next + imm;
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
if ((next_pc & 0x3) != 0) {
gen_exception_inst_addr_mis(ctx);
TCGv target_pc = tcg_temp_new();
gen_pc_plus_diff(target_pc, ctx, next_pc);
gen_exception_inst_addr_mis(ctx, target_pc);
return;
}
}