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ati-vga: Add 30 bit palette access register

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Radeon cards have a 30 bit DAC and corresponding palette register to
access it. We only use 8 bits but let the guests use 10 bit color
values for those that access it through this register.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <9fa19eec95d1563cc65853cf26912f230c702b32.1698871239.git.balaton@eik.bme.hu>
This commit is contained in:
BALATON Zoltan 2023-11-01 21:45:38 +01:00 • committed by Marc-André Lureau
parent e876b3400a
commit bf9ac62a92
4 changed files with 12 additions and 0 deletions
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9
hw/display/ati.c
View file

@ -339,6 +339,9 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size)
case PALETTE_DATA: case PALETTE_DATA:
val = vga_ioport_read(&s->vga, VGA_PEL_D); val = vga_ioport_read(&s->vga, VGA_PEL_D);
break; break;
case PALETTE_30_DATA:
val = s->regs.palette[vga_ioport_read(&s->vga, VGA_PEL_IR)];
break;
case CNFG_CNTL: case CNFG_CNTL:
val = s->regs.config_cntl; val = s->regs.config_cntl;
break; break;
@ -673,6 +676,12 @@ static void ati_mm_write(void *opaque, hwaddr addr,
data >>= 8; data >>= 8;
vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
break; break;
case PALETTE_30_DATA:
s->regs.palette[vga_ioport_read(&s->vga, VGA_PEL_IW)] = data;
vga_ioport_write(&s->vga, VGA_PEL_D, (data >> 22) & 0xff);
vga_ioport_write(&s->vga, VGA_PEL_D, (data >> 12) & 0xff);
vga_ioport_write(&s->vga, VGA_PEL_D, (data >> 2) & 0xff);
break;
case CNFG_CNTL: case CNFG_CNTL:
s->regs.config_cntl = data; s->regs.config_cntl = data;
break; break;

1
hw/display/ati_dbg.c
View file

@ -30,6 +30,7 @@ static struct ati_regdesc ati_reg_names[] = {
{"AMCGPIO_EN_MIR", 0x00a8}, {"AMCGPIO_EN_MIR", 0x00a8},
{"PALETTE_INDEX", 0x00b0}, {"PALETTE_INDEX", 0x00b0},
{"PALETTE_DATA", 0x00b4}, {"PALETTE_DATA", 0x00b4},
{"PALETTE_30_DATA", 0x00b8},
{"CNFG_CNTL", 0x00e0}, {"CNFG_CNTL", 0x00e0},
{"GEN_RESET_CNTL", 0x00f0}, {"GEN_RESET_CNTL", 0x00f0},
{"CNFG_MEMSIZE", 0x00f8}, {"CNFG_MEMSIZE", 0x00f8},

1
hw/display/ati_int.h
View file

@ -44,6 +44,7 @@ typedef struct ATIVGARegs {
uint32_t gpio_dvi_ddc; uint32_t gpio_dvi_ddc;
uint32_t gpio_monid; uint32_t gpio_monid;
uint32_t config_cntl; uint32_t config_cntl;
uint32_t palette[256];
uint32_t crtc_h_total_disp; uint32_t crtc_h_total_disp;
uint32_t crtc_h_sync_strt_wid; uint32_t crtc_h_sync_strt_wid;
uint32_t crtc_v_total_disp; uint32_t crtc_v_total_disp;

1
hw/display/ati_regs.h
View file

@ -48,6 +48,7 @@
#define AMCGPIO_EN_MIR 0x00a8 #define AMCGPIO_EN_MIR 0x00a8
#define PALETTE_INDEX 0x00b0 #define PALETTE_INDEX 0x00b0
#define PALETTE_DATA 0x00b4 #define PALETTE_DATA 0x00b4
#define PALETTE_30_DATA 0x00b8
#define CNFG_CNTL 0x00e0 #define CNFG_CNTL 0x00e0
#define GEN_RESET_CNTL 0x00f0 #define GEN_RESET_CNTL 0x00f0
#define CNFG_MEMSIZE 0x00f8 #define CNFG_MEMSIZE 0x00f8