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target/riscv: Restrict SoftMMU mmu_index() to TCG

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Move riscv_cpu_mmu_index() to the TCG-specific file,
convert CPUClass::mmu_index() to TCGCPUOps::mmu_index().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250401080938.32278-17-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-04-01 10:09:29 +02:00 • committed by Richard Henderson
parent 853f9378a3
commit bf8dc33bbc
2 changed files with 6 additions and 6 deletions
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6
target/riscv/cpu.c
View file

@ -1021,11 +1021,6 @@ bool riscv_cpu_has_work(CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch)
{
return riscv_env_mmu_index(cpu_env(cs), ifetch);
}
static void riscv_cpu_reset_hold(Object *obj, ResetType type)
{
#ifndef CONFIG_USER_ONLY
@ -3049,7 +3044,6 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
&mcc->parent_phases);
cc->class_by_name = riscv_cpu_class_by_name;
cc->mmu_index = riscv_cpu_mmu_index;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
cc->get_pc = riscv_cpu_get_pc;

6
target/riscv/tcg/tcg-cpu.c
View file

@ -91,6 +91,11 @@ static const char *cpu_priv_ver_to_str(int priv_ver)
return priv_spec_str;
}
static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch)
{
return riscv_env_mmu_index(cpu_env(cs), ifetch);
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@ -138,6 +143,7 @@ static const TCGCPUOps riscv_tcg_ops = {
.translate_code = riscv_translate_code,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
.restore_state_to_opc = riscv_restore_state_to_opc,
.mmu_index = riscv_cpu_mmu_index,
#ifndef CONFIG_USER_ONLY
.tlb_fill = riscv_cpu_tlb_fill,