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hw/arm/aspeed: Add GB200 BMC target
GB200nvl72 is a system for for accelerated compute. This is a model for the BMC target within the system. This is based on the device tree aspeed-bmc-nvidia-gb200nvl-bmc.dts from: [1] https://github.com/openbmc/linux/blob/dev-6.6/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-4-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Ed Tanous
Cédric Le Goater
parent
ad8e0e8a00
commit
becfaa10a2
3 changed files with 102 additions and 0 deletions
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@ -201,6 +201,10 @@ struct AspeedMachineState {
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#define BLETCHLEY_BMC_HW_STRAP1 0x00002000
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#define BLETCHLEY_BMC_HW_STRAP2 0x00000801
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/* GB200NVL hardware value */
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#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
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#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
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/* Qualcomm DC-SCM hardware value */
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#define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
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#define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
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@ -647,6 +651,12 @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
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TYPE_PCA9552, addr);
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}
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static I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr)
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{
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return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
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TYPE_PCA9554, addr);
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}
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static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
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{
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AspeedSoCState *soc = bmc->soc;
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@ -1226,6 +1236,45 @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
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i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
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}
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static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
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{
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AspeedSoCState *soc = bmc->soc;
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I2CBus *i2c[15] = {};
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DeviceState *dev;
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for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) {
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if ((i == 11) || (i == 12) || (i == 13)) {
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continue;
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}
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i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
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}
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/* Bus 5 Expander */
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create_pca9554(soc, 4, 0x21);
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/* Mux I2c Expanders */
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i2c_slave_create_simple(i2c[5], "pca9546", 0x71);
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i2c_slave_create_simple(i2c[5], "pca9546", 0x72);
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i2c_slave_create_simple(i2c[5], "pca9546", 0x73);
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i2c_slave_create_simple(i2c[5], "pca9546", 0x75);
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i2c_slave_create_simple(i2c[5], "pca9546", 0x76);
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i2c_slave_create_simple(i2c[5], "pca9546", 0x77);
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/* Bus 10 */
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dev = DEVICE(create_pca9554(soc, 9, 0x20));
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/* Set FPGA_READY */
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object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal);
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create_pca9554(soc, 9, 0x21);
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at24c_eeprom_init(i2c[9], 0x50, 64 * KiB);
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at24c_eeprom_init(i2c[9], 0x51, 64 * KiB);
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/* Bus 11 */
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at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid,
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gb200nvl_bmc_fruid_len);
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}
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static void fby35_i2c_init(AspeedMachineState *bmc)
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{
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AspeedSoCState *soc = bmc->soc;
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@ -1782,6 +1831,31 @@ static void aspeed_machine_catalina_class_init(ObjectClass *oc,
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aspeed_machine_ast2600_class_emmc_init(oc);
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}
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#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB)
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static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
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const void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
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mc->desc = "Nvidia GB200NVL BMC (Cortex-A7)";
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amc->soc_name = "ast2600-a3";
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amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1;
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amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2;
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amc->fmc_model = "mx66u51235f";
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amc->spi_model = "mx66u51235f";
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amc->num_cs = 2;
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amc->spi2_model = "mx66u51235f";
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amc->num_cs2 = 1;
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amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
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amc->i2c_init = gb200nvl_bmc_i2c_init;
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mc->default_ram_size = GB200NVL_BMC_RAM_SIZE;
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aspeed_machine_class_init_cpus_defaults(mc);
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aspeed_machine_ast2600_class_emmc_init(oc);
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}
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static void fby35_reset(MachineState *state, ResetType type)
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{
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AspeedMachineState *bmc = ASPEED_MACHINE(state);
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@ -2074,6 +2148,10 @@ static const TypeInfo aspeed_machine_types[] = {
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.name = MACHINE_TYPE_NAME("bletchley-bmc"),
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.parent = TYPE_ASPEED_MACHINE,
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.class_init = aspeed_machine_bletchley_class_init,
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}, {
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.name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
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.parent = TYPE_ASPEED_MACHINE,
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.class_init = aspeed_machine_gb200nvl_class_init,
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}, {
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.name = MACHINE_TYPE_NAME("catalina-bmc"),
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.parent = TYPE_ASPEED_MACHINE,
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@ -162,6 +162,25 @@ const uint8_t rainier_bmc_fruid[] = {
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0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
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};
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const uint8_t gb200nvl_bmc_fruid[] = {
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0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f,
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0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33,
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0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38,
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0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33,
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0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30,
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0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a,
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0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a,
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0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44,
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0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43,
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0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30,
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0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31,
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0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31,
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0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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};
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const size_t tiogapass_bmc_fruid_len = sizeof(tiogapass_bmc_fruid);
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const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
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const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
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@ -169,3 +188,5 @@ const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
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const size_t yosemitev2_bmc_fruid_len = sizeof(yosemitev2_bmc_fruid);
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const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid);
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const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid);
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const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid);
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@ -26,4 +26,7 @@ extern const size_t rainier_bb_fruid_len;
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extern const uint8_t rainier_bmc_fruid[];
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extern const size_t rainier_bmc_fruid_len;
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extern const uint8_t gb200nvl_bmc_fruid[];
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extern const size_t gb200nvl_bmc_fruid_len;
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#endif
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