mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 08:13:54 -06:00
target/arm: Pass more cpu state to arm_excp_unmasked
Avoid redundant computation of cpu state by passing it in from the caller, which has already computed it for itself. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-40-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
310cedf39d
commit
be87955687
1 changed files with 12 additions and 10 deletions
|
@ -411,14 +411,13 @@ static void arm_cpu_reset(CPUState *s)
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
|
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
|
||||||
unsigned int target_el)
|
unsigned int target_el,
|
||||||
|
unsigned int cur_el, bool secure,
|
||||||
|
uint64_t hcr_el2)
|
||||||
{
|
{
|
||||||
CPUARMState *env = cs->env_ptr;
|
CPUARMState *env = cs->env_ptr;
|
||||||
unsigned int cur_el = arm_current_el(env);
|
|
||||||
bool secure = arm_is_secure(env);
|
|
||||||
bool pstate_unmasked;
|
bool pstate_unmasked;
|
||||||
int8_t unmasked = 0;
|
int8_t unmasked = 0;
|
||||||
uint64_t hcr_el2;
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Don't take exceptions if they target a lower EL.
|
* Don't take exceptions if they target a lower EL.
|
||||||
|
@ -429,8 +428,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
hcr_el2 = arm_hcr_el2_eff(env);
|
|
||||||
|
|
||||||
switch (excp_idx) {
|
switch (excp_idx) {
|
||||||
case EXCP_FIQ:
|
case EXCP_FIQ:
|
||||||
pstate_unmasked = !(env->daif & PSTATE_F);
|
pstate_unmasked = !(env->daif & PSTATE_F);
|
||||||
|
@ -535,6 +532,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
||||||
CPUARMState *env = cs->env_ptr;
|
CPUARMState *env = cs->env_ptr;
|
||||||
uint32_t cur_el = arm_current_el(env);
|
uint32_t cur_el = arm_current_el(env);
|
||||||
bool secure = arm_is_secure(env);
|
bool secure = arm_is_secure(env);
|
||||||
|
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
|
||||||
uint32_t target_el;
|
uint32_t target_el;
|
||||||
uint32_t excp_idx;
|
uint32_t excp_idx;
|
||||||
bool ret = false;
|
bool ret = false;
|
||||||
|
@ -542,7 +540,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
||||||
if (interrupt_request & CPU_INTERRUPT_FIQ) {
|
if (interrupt_request & CPU_INTERRUPT_FIQ) {
|
||||||
excp_idx = EXCP_FIQ;
|
excp_idx = EXCP_FIQ;
|
||||||
target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
|
target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
|
||||||
if (arm_excp_unmasked(cs, excp_idx, target_el)) {
|
if (arm_excp_unmasked(cs, excp_idx, target_el,
|
||||||
|
cur_el, secure, hcr_el2)) {
|
||||||
cs->exception_index = excp_idx;
|
cs->exception_index = excp_idx;
|
||||||
env->exception.target_el = target_el;
|
env->exception.target_el = target_el;
|
||||||
cc->do_interrupt(cs);
|
cc->do_interrupt(cs);
|
||||||
|
@ -552,7 +551,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
||||||
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
||||||
excp_idx = EXCP_IRQ;
|
excp_idx = EXCP_IRQ;
|
||||||
target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
|
target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
|
||||||
if (arm_excp_unmasked(cs, excp_idx, target_el)) {
|
if (arm_excp_unmasked(cs, excp_idx, target_el,
|
||||||
|
cur_el, secure, hcr_el2)) {
|
||||||
cs->exception_index = excp_idx;
|
cs->exception_index = excp_idx;
|
||||||
env->exception.target_el = target_el;
|
env->exception.target_el = target_el;
|
||||||
cc->do_interrupt(cs);
|
cc->do_interrupt(cs);
|
||||||
|
@ -562,7 +562,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
||||||
if (interrupt_request & CPU_INTERRUPT_VIRQ) {
|
if (interrupt_request & CPU_INTERRUPT_VIRQ) {
|
||||||
excp_idx = EXCP_VIRQ;
|
excp_idx = EXCP_VIRQ;
|
||||||
target_el = 1;
|
target_el = 1;
|
||||||
if (arm_excp_unmasked(cs, excp_idx, target_el)) {
|
if (arm_excp_unmasked(cs, excp_idx, target_el,
|
||||||
|
cur_el, secure, hcr_el2)) {
|
||||||
cs->exception_index = excp_idx;
|
cs->exception_index = excp_idx;
|
||||||
env->exception.target_el = target_el;
|
env->exception.target_el = target_el;
|
||||||
cc->do_interrupt(cs);
|
cc->do_interrupt(cs);
|
||||||
|
@ -572,7 +573,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
||||||
if (interrupt_request & CPU_INTERRUPT_VFIQ) {
|
if (interrupt_request & CPU_INTERRUPT_VFIQ) {
|
||||||
excp_idx = EXCP_VFIQ;
|
excp_idx = EXCP_VFIQ;
|
||||||
target_el = 1;
|
target_el = 1;
|
||||||
if (arm_excp_unmasked(cs, excp_idx, target_el)) {
|
if (arm_excp_unmasked(cs, excp_idx, target_el,
|
||||||
|
cur_el, secure, hcr_el2)) {
|
||||||
cs->exception_index = excp_idx;
|
cs->exception_index = excp_idx;
|
||||||
env->exception.target_el = target_el;
|
env->exception.target_el = target_el;
|
||||||
cc->do_interrupt(cs);
|
cc->do_interrupt(cs);
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue