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ppc/pnv: Add QME region for P10

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The Quad Management Engine (QME) manages power related settings for its
quad. The xscom region is separate from the quad xscoms, therefore a new
region is added. The xscoms in a QME select a given core by selecting
the forth nibble.

Implement dummy reads for the stop state history (SSH) and special
wakeup (SPWU) registers. This quietens some sxcom errors when skiboot
boots on p10.

Power9 does not have a QME.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-ID: <20230707071213.9924-1-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Joel Stanley 2023-07-07 16:42:13 +09:30 • committed by Daniel Henrique Barboza
parent 9c1ce7723b
commit bdb97596f6
4 changed files with 94 additions and 2 deletions
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4
include/hw/ppc/pnv_core.h
View file

@ -66,6 +66,9 @@ struct PnvQuadClass {
const MemoryRegionOps *xscom_ops;
uint64_t xscom_size;
const MemoryRegionOps *xscom_qme_ops;
uint64_t xscom_qme_size;
};
#define TYPE_PNV_QUAD "powernv-cpu-quad"
@ -80,5 +83,6 @@ struct PnvQuad {
uint32_t quad_id;
MemoryRegion xscom_regs;
MemoryRegion xscom_qme_regs;
};
#endif /* PPC_PNV_CORE_H */

11
include/hw/ppc/pnv_xscom.h
View file

@ -127,6 +127,17 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_EC(proc) \
((0x2 << 16) | ((1 << (3 - (proc))) << 12))
#define PNV10_XSCOM_QME(chiplet) \
(PNV10_XSCOM_EQ(chiplet) | (0xE << 16))
/*
* Make the region larger by 0x1000 (instead of starting at an offset) so the
* modelled addresses start from 0
*/
#define PNV10_XSCOM_QME_BASE(core) \
((uint64_t) PNV10_XSCOM_QME(PNV10_XSCOM_EQ_CHIPLET(core)))
#define PNV10_XSCOM_QME_SIZE (0x8000 + 0x1000)
#define PNV10_XSCOM_EQ_BASE(core) \
((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
#define PNV10_XSCOM_EQ_SIZE 0x20000