motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 08:13:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: Add the Hypervisor CSRs to CPUState

Browse source 
Add the Hypervisor CSRs to CPUState and at the same time (to avoid
bisect issues) update the CSR macros for the v0.5 Hyp spec.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Alistair Francis 2020-01-31 17:01:43 -08:00 • committed by Palmer Dabbelt
parent af1fa0039c
commit bd023ce33b
No known key found for this signature in database
GPG key ID: 2E1319F35FBB1889
3 changed files with 48 additions and 18 deletions
Download patch file Download diff file Expand all files Collapse all files

11
target/riscv/gdbstub.c
View file

@ -130,6 +130,8 @@ static int csr_register_map[] = {
CSR_MCAUSE,
CSR_MTVAL,
CSR_MIP,
CSR_MTINST,
CSR_MTVAL2,
CSR_PMPCFG0,
CSR_PMPCFG1,
CSR_PMPCFG2,
@ -252,12 +254,11 @@ static int csr_register_map[] = {
CSR_HEDELEG,
CSR_HIDELEG,
CSR_HIE,
CSR_HTVEC,
CSR_HSCRATCH,
CSR_HEPC,
CSR_HCAUSE,
CSR_HBADADDR,
CSR_HCOUNTEREN,
CSR_HTVAL,
CSR_HIP,
CSR_HTINST,
CSR_HGATP,
CSR_MBASE,
CSR_MBOUND,
CSR_MIBASE,