From 8a1975e4d44b56124dcf37e972e645ba21b3722b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Tue, 3 Jun 2025 12:01:48 +0100 Subject: [PATCH 01/11] tests/docker: expose $HOME/.cache/qemu as docker volume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If you want to run functional tests we should share .cache/qemu so we don't force containers to continually re-download images. We also move ccache to use this shared area. Reviewed-by: Thomas Huth Signed-off-by: Alex Bennée Message-ID: <20250603110204.838117-2-alex.bennee@linaro.org> --- tests/docker/Makefile.include | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index fa1cbb6726..3959d8a028 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -185,8 +185,10 @@ docker: docker-help: docker +# Where QEMU caches build artefacts +DOCKER_QEMU_CACHE_DIR := $$HOME/.cache/qemu # Use a global constant ccache directory to speed up repetitive builds -DOCKER_CCACHE_DIR := $$HOME/.cache/qemu-docker-ccache +DOCKER_QEMU_CCACHE_DIR := DOCKER_QEMU_CACHE_DIR/docker-ccache # This rule if for directly running against an arbitrary docker target. # It is called by the expanded docker targets (e.g. make @@ -195,7 +197,7 @@ DOCKER_CCACHE_DIR := $$HOME/.cache/qemu-docker-ccache # For example: make docker-run TEST="test-quick" IMAGE="debian:arm64" EXECUTABLE=./aarch64-linux-user/qemu-aarch64 # docker-run: docker-qemu-src - @mkdir -p "$(DOCKER_CCACHE_DIR)" + @mkdir -p "$(DOCKER_QEMU_CCACHE_DIR)" @if test -z "$(IMAGE)" || test -z "$(TEST)"; \ then echo "Invalid target $(IMAGE)/$(TEST)"; exit 1; \ fi @@ -222,8 +224,8 @@ docker-run: docker-qemu-src -e V=$V -e J=$J -e DEBUG=$(DEBUG) \ -e SHOW_ENV=$(SHOW_ENV) \ $(if $(NOUSER),, \ - -e CCACHE_DIR=/var/tmp/ccache \ - -v $(DOCKER_CCACHE_DIR):/var/tmp/ccache:z \ + -v $(DOCKER_QEMU_CACHE_DIR):$(DOCKER_QEMU_CACHE_DIR) \ + -e CCACHE_DIR=$(DOCKER_QEMU_CCACHE_DIR) \ ) \ -v $$(readlink -e $(DOCKER_SRC_COPY)):/var/tmp/qemu:z$(COMMA)ro \ $(IMAGE) \ From cfd7ebd9b0dc18168cd97f12aeb0782ac0adf869 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Tue, 3 Jun 2025 12:01:49 +0100 Subject: [PATCH 02/11] gitlab: disable debug info on CI builds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Our default build enables debug info which adds hugely to the size of the builds as well as the size of cached objects. Disable debug info across the board to save space and reduce pressure on the CI system. We still have a number of builds which explicitly enable debug and related extra asserts like --enable-debug-tcg. Reviewed-by: Thomas Huth Signed-off-by: Alex Bennée Message-ID: <20250603110204.838117-3-alex.bennee@linaro.org> --- .gitlab-ci.d/buildtest-template.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.d/buildtest-template.yml b/.gitlab-ci.d/buildtest-template.yml index fea4e8da2f..038c3c9540 100644 --- a/.gitlab-ci.d/buildtest-template.yml +++ b/.gitlab-ci.d/buildtest-template.yml @@ -24,6 +24,7 @@ - ccache --zero-stats - section_start configure "Running configure" - ../configure --enable-werror --disable-docs --enable-fdt=system + --disable-debug-info ${TARGETS:+--target-list="$TARGETS"} $CONFIGURE_ARGS || { cat config.log meson-logs/meson-log.txt && exit 1; } From 4f5c81844c3b9185ad1cf80c1e17b05ec22e944a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Tue, 3 Jun 2025 12:01:50 +0100 Subject: [PATCH 03/11] tests/tcg: make aarch64 boot.S handle different starting modes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently the boot.S code assumes everything starts at EL1. This will break things like the memory test which will barf on unaligned memory access when run at a higher level. Adapt the boot code to do some basic verification of the starting mode and the minimal configuration to move to the lower exception levels. With this we can run the memory test with: -M virt,secure=on -M virt,secure=on,virtualization=on -M virt,virtualisation=on If a test needs to be at a particular EL it can use the semihosting command line to indicate the level we should execute in. Cc: Julian Armistead Cc: Jim MacArthur Signed-off-by: Alex Bennée Message-ID: <20250603110204.838117-4-alex.bennee@linaro.org> --- tests/tcg/aarch64/Makefile.softmmu-target | 3 +- tests/tcg/aarch64/system/boot.S | 172 +++++++++++++++++++++- 2 files changed, 169 insertions(+), 6 deletions(-) diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index 9c52475b7a..f7a7d2b800 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -68,7 +68,8 @@ run-plugin-semiconsole-with-%: semiconsole # vtimer test needs EL2 QEMU_EL2_MACHINE=-machine virt,virtualization=on,gic-version=2 -cpu cortex-a57 -smp 4 -run-vtimer: QEMU_OPTS=$(QEMU_EL2_MACHINE) $(QEMU_BASE_ARGS) -kernel +QEMU_EL2_BASE_ARGS=-semihosting-config enable=on,target=native,chardev=output,arg="2" +run-vtimer: QEMU_OPTS=$(QEMU_EL2_MACHINE) $(QEMU_EL2_BASE_ARGS) -kernel # Simple Record/Replay Test .PHONY: memory-record diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boot.S index a5df9c173d..8bfa4e4efc 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -16,6 +16,7 @@ #define semihosting_call hlt 0xf000 #define SYS_WRITEC 0x03 /* character to debug channel */ #define SYS_WRITE0 0x04 /* string to debug channel */ +#define SYS_GET_CMDLINE 0x15 /* get command line */ #define SYS_EXIT 0x18 .align 12 @@ -70,21 +71,172 @@ lower_a32_sync: lower_a32_irq: lower_a32_fiq: lower_a32_serror: + adr x1, .unexp_excp +exit_msg: mov x0, SYS_WRITE0 - adr x1, .error semihosting_call mov x0, 1 /* EXIT_FAILURE */ bl _exit /* never returns */ .section .rodata -.error: - .string "Terminated by exception.\n" +.unexp_excp: + .string "Unexpected exception.\n" +.high_el_msg: + .string "Started in lower EL than requested.\n" +.unexp_el0: + .string "Started in invalid EL.\n" + + .align 8 +.get_cmd: + .quad cmdline + .quad 128 .text .align 4 .global __start __start: + /* + * Initialise the stack for whatever EL we are in before + * anything else, we need it to be able to _exit cleanly. + * It's smaller than the stack we pass to the C code but we + * don't need much. + */ + adrp x0, system_stack_end + add x0, x0, :lo12:system_stack_end + mov sp, x0 + + /* + * The test can set the semihosting command line to the target + * EL needed for the test. However if no semihosting args are set we will + * end up with -kernel/-append data (see semihosting_arg_fallback). + * Keep the normalised target in w11. + */ + mov x0, SYS_GET_CMDLINE + adr x1, .get_cmd + semihosting_call + adrp x10, cmdline + add x10, x10, :lo12:cmdline + ldrb w11, [x10] + + /* sanity check, normalise char to EL, clamp to 1 if outside range */ + subs w11, w11, #'0' + b.lt el_default + cmp w11, #3 + b.gt el_default + b 1f + +el_high: + adr x1, .high_el_msg + b exit_msg + +el_default: + mov w11, #1 + +1: + /* Determine current Exception Level */ + mrs x0, CurrentEL + lsr x0, x0, #2 /* CurrentEL[3:2] contains the current EL */ + + /* Are we already in a lower EL than we want? */ + cmp w11, w0 + bgt el_high + + /* Branch based on current EL */ + cmp x0, #3 + b.eq setup_el3 + cmp x0, #2 + b.eq setup_el2 + cmp x0, #1 + b.eq at_testel /* Already at EL1, skip transition */ + + /* Should not be at EL0 - error out */ + adr x1, .unexp_el0 + b exit_msg + +setup_el3: + /* Ensure we trap if we get anything wrong */ + adr x0, vector_table + msr vbar_el3, x0 + + /* Does the test want to be at EL3? */ + cmp w11, #3 + beq at_testel + + /* Configure EL3 to for lower states (EL2 or EL1) */ + mrs x0, scr_el3 + orr x0, x0, #(1 << 10) /* RW = 1: EL2/EL1 execution state is AArch64 */ + orr x0, x0, #(1 << 0) /* NS = 1: Non-secure state */ + msr scr_el3, x0 + + /* + * We need to check if EL2 is actually enabled via ID_AA64PFR0_EL1, + * otherwise we should just jump straight to EL1. + */ + mrs x0, id_aa64pfr0_el1 + ubfx x0, x0, #8, #4 /* Extract EL2 field (bits 11:8) */ + cbz x0, el2_not_present /* If field is 0 no EL2 */ + + + /* Prepare SPSR for exception return to EL2 */ + mov x0, #0x3c9 /* DAIF bits and EL2h mode (9) */ + msr spsr_el3, x0 + + /* Set EL2 entry point */ + adr x0, setup_el2 + msr elr_el3, x0 + + /* Return to EL2 */ + eret + +el2_not_present: + /* Initialize SCTLR_EL1 with reset value */ + msr sctlr_el1, xzr + + /* Set EL1 entry point */ + adr x0, at_testel + msr elr_el3, x0 + + /* Prepare SPSR for exception return to EL1h with interrupts masked */ + mov x0, #0x3c5 /* DAIF bits and EL1h mode (5) */ + msr spsr_el3, x0 + + isb /* Synchronization barrier */ + eret /* Jump to EL1 */ + +setup_el2: + /* Ensure we trap if we get anything wrong */ + adr x0, vector_table + msr vbar_el2, x0 + + /* Does the test want to be at EL2? */ + cmp w11, #2 + beq at_testel + + /* Configure EL2 to allow transition to EL1 */ + mrs x0, hcr_el2 + orr x0, x0, #(1 << 31) /* RW = 1: EL1 execution state is AArch64 */ + msr hcr_el2, x0 + + /* Initialize SCTLR_EL1 with reset value */ + msr sctlr_el1, xzr + + /* Set EL1 entry point */ + adr x0, at_testel + msr elr_el2, x0 + + /* Prepare SPSR for exception return to EL1 */ + mov x0, #(0x5 << 0) /* EL1h (SPx), with interrupts disabled */ + msr spsr_el2, x0 + + /* Return to EL1 */ + eret + + /* + * At the target EL for the test, usually EL1. Note we still + * set everything up as if we were at EL1. + */ +at_testel: /* Installs a table of exception vectors to catch and handle all exceptions by terminating the process with a diagnostic. */ adr x0, vector_table @@ -100,7 +252,7 @@ __start: * maps RAM to the first Gb. The stage2 tables have two 2mb * translation block entries covering a series of adjacent * 4k pages. - */ + */ /* Stage 1 entry: indexed by IA[38:30] */ adr x1, . /* phys address */ @@ -198,7 +350,8 @@ __start: orr x0, x0, #(3 << 16) msr cpacr_el1, x0 - /* Setup some stack space and enter the test code. + /* + * Setup some stack space before we enter the test code. * Assume everything except the return value is garbage when we * return, we won't need it. */ @@ -233,6 +386,11 @@ __sys_outc: ret .data + + .align 8 +cmdline: + .space 128, 0 + .align 12 /* Translation table @@ -246,6 +404,10 @@ ttb_stage2: .space 4096, 0 .align 12 +system_stack: + .space 4096, 0 +system_stack_end: + stack: .space 65536, 0 stack_end: From 26b20dc20745d68c7a425326f189ae0ca91bf1d6 Mon Sep 17 00:00:00 2001 From: Nabih Estefan Date: Tue, 3 Jun 2025 12:01:51 +0100 Subject: [PATCH 04/11] tests/qtest: Avoid unaligned access in IGB test MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ../tests/qtest/libqos/igb.c:106:5: runtime error: load of misaligned address 0x562040be8e33 for type 'uint32_t', which requires 4 byte alignment Instead of straight casting the uint8_t array, we can use ldl_le_p and lduw_l_p to assure the unaligned access works properly against uint32_t and uint16_t. Signed-off-by: Nabih Estefan Reviewed-by: Laurent Vivier Tested-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20250429155621.2028198-1-nabihestefan@google.com> [AJB: fix commit message, remove unneeded casts] Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée Reviewed-by: Akihiko Odaki Message-ID: <20250603110204.838117-5-alex.bennee@linaro.org> --- tests/qtest/libqos/igb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/qtest/libqos/igb.c b/tests/qtest/libqos/igb.c index f40c4ec4cd..ab3ef6f0c3 100644 --- a/tests/qtest/libqos/igb.c +++ b/tests/qtest/libqos/igb.c @@ -104,10 +104,10 @@ static void igb_pci_start_hw(QOSGraphObject *obj) e1000e_macreg_write(&d->e1000e, E1000_RDT(0), 0); e1000e_macreg_write(&d->e1000e, E1000_RDH(0), 0); e1000e_macreg_write(&d->e1000e, E1000_RA, - le32_to_cpu(*(uint32_t *)address)); + ldl_le_p(address)); e1000e_macreg_write(&d->e1000e, E1000_RA + 4, E1000_RAH_AV | E1000_RAH_POOL_1 | - le16_to_cpu(*(uint16_t *)(address + 4))); + lduw_le_p(address + 4)); /* Set supported receive descriptor mode */ e1000e_macreg_write(&d->e1000e, From 0dd99ef2502be9097afd969aa1071fec57db600a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Tue, 3 Jun 2025 12:01:52 +0100 Subject: [PATCH 05/11] contrib/plugins: add a scaling factor to the ips arg MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's easy to get lost in zeros while setting the numbers of instructions per second. Add a scaling suffix to make things simpler. Reviewed-by: Pierrick Bouvier Signed-off-by: Alex Bennée Message-ID: <20250603110204.838117-6-alex.bennee@linaro.org> --- contrib/plugins/ips.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/contrib/plugins/ips.c b/contrib/plugins/ips.c index e5297dbb01..d067971135 100644 --- a/contrib/plugins/ips.c +++ b/contrib/plugins/ips.c @@ -129,6 +129,18 @@ static void plugin_exit(qemu_plugin_id_t id, void *udata) qemu_plugin_scoreboard_free(vcpus); } +typedef struct { + const char *suffix; + unsigned long multipler; +} ScaleEntry; + +/* a bit like units.h but not binary */ +static const ScaleEntry scales[] = { + { "k", 1000 }, + { "m", 1000 * 1000 }, + { "g", 1000 * 1000 * 1000 }, +}; + QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id, const qemu_info_t *info, int argc, char **argv) @@ -137,12 +149,32 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id, char *opt = argv[i]; g_auto(GStrv) tokens = g_strsplit(opt, "=", 2); if (g_strcmp0(tokens[0], "ips") == 0) { - max_insn_per_second = g_ascii_strtoull(tokens[1], NULL, 10); + char *endptr = NULL; + max_insn_per_second = g_ascii_strtoull(tokens[1], &endptr, 10); if (!max_insn_per_second && errno) { fprintf(stderr, "%s: couldn't parse %s (%s)\n", __func__, tokens[1], g_strerror(errno)); return -1; } + + if (endptr && *endptr != 0) { + g_autofree gchar *lower = g_utf8_strdown(endptr, -1); + unsigned long scale = 0; + + for (int j = 0; j < G_N_ELEMENTS(scales); j++) { + if (g_strcmp0(lower, scales[j].suffix) == 0) { + scale = scales[j].multipler; + break; + } + } + + if (scale) { + max_insn_per_second *= scale; + } else { + fprintf(stderr, "bad suffix: %s\n", endptr); + return -1; + } + } } else { fprintf(stderr, "option parsing failed: %s\n", opt); return -1; From 002655381f126a9266e0d378ebebbe87cb257a6a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Tue, 3 Jun 2025 12:01:53 +0100 Subject: [PATCH 06/11] contrib/plugins: allow setting of instructions per quantum MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The default is we update time every 1/10th of a second or so. However for some cases we might want to update time more frequently. Allow this to be set via the command line through the ipq argument. Reviewed-by: Pierrick Bouvier Signed-off-by: Alex Bennée Message-ID: <20250603110204.838117-7-alex.bennee@linaro.org> --- contrib/plugins/ips.c | 15 ++++++++++++++- docs/about/emulation.rst | 4 ++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/contrib/plugins/ips.c b/contrib/plugins/ips.c index d067971135..f110c565bc 100644 --- a/contrib/plugins/ips.c +++ b/contrib/plugins/ips.c @@ -145,6 +145,8 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id, const qemu_info_t *info, int argc, char **argv) { + bool ipq_set = false; + for (int i = 0; i < argc; i++) { char *opt = argv[i]; g_auto(GStrv) tokens = g_strsplit(opt, "=", 2); @@ -175,6 +177,14 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id, return -1; } } + } else if (g_strcmp0(tokens[0], "ipq") == 0) { + max_insn_per_quantum = g_ascii_strtoull(tokens[1], NULL, 10); + + if (!max_insn_per_quantum) { + fprintf(stderr, "bad ipq value: %s\n", tokens[0]); + return -1; + } + ipq_set = true; } else { fprintf(stderr, "option parsing failed: %s\n", opt); return -1; @@ -182,7 +192,10 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id, } vcpus = qemu_plugin_scoreboard_new(sizeof(vCPUTime)); - max_insn_per_quantum = max_insn_per_second / NUM_TIME_UPDATE_PER_SEC; + + if (!ipq_set) { + max_insn_per_quantum = max_insn_per_second / NUM_TIME_UPDATE_PER_SEC; + } if (max_insn_per_quantum == 0) { fprintf(stderr, "minimum of %d instructions per second needed\n", diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst index a72591ee4d..456d01d5b0 100644 --- a/docs/about/emulation.rst +++ b/docs/about/emulation.rst @@ -811,6 +811,10 @@ This plugin can limit the number of Instructions Per Second that are executed:: * - ips=N - Maximum number of instructions per cpu that can be executed in one second. The plugin will sleep when the given number of instructions is reached. + * - ipq=N + - Instructions per quantum. How many instructions before we re-calculate time. + The lower the number the more accurate time will be, but the less efficient the plugin. + Defaults to ips/10 Other emulation features ------------------------ From 7aabb6dbba30f0c2bcedbd5593e1292d4d791244 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Tue, 3 Jun 2025 12:02:00 +0100 Subject: [PATCH 07/11] include/exec: fix assert in size_memop MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can handle larger sized memops now, expand the range of the assert. Fixes: 4b473e0c60 (tcg: Expand MO_SIZE to 3 bits) Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Message-ID: <20250603110204.838117-14-alex.bennee@linaro.org> --- include/exec/memop.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 407a47d82c..cf7da3362e 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -162,8 +162,8 @@ static inline unsigned memop_size(MemOp op) static inline MemOp size_memop(unsigned size) { #ifdef CONFIG_DEBUG_TCG - /* Power of 2 up to 8. */ - assert((size & (size - 1)) == 0 && size >= 1 && size <= 8); + /* Power of 2 up to 1024 */ + assert(is_power_of_2(size) && size >= 1 && size <= (1 << MO_SIZE)); #endif return (MemOp)ctz32(size); } From 46b17eb9e261f28697a6fa5cb09c5fc505ef68ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Tue, 3 Jun 2025 12:02:01 +0100 Subject: [PATCH 08/11] include/gdbstub: fix include guard in commands.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée Message-ID: <20250603110204.838117-15-alex.bennee@linaro.org> --- include/gdbstub/commands.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/gdbstub/commands.h b/include/gdbstub/commands.h index 40f0514fe9..bff3674872 100644 --- a/include/gdbstub/commands.h +++ b/include/gdbstub/commands.h @@ -1,5 +1,5 @@ #ifndef GDBSTUB_COMMANDS_H -#define GDBSTUB +#define GDBSTUB_COMMANDS_H typedef void (*GdbCmdHandler)(GArray *params, void *user_ctx); From 3bb69b1953c1a829152ff5c2599269bc129e05ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Tue, 3 Jun 2025 12:02:02 +0100 Subject: [PATCH 09/11] gdbstub: assert earlier in handle_read_all_regs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When things go wrong we want to assert on the register that failed to be able to figure out what went wrong. Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée Message-ID: <20250603110204.838117-16-alex.bennee@linaro.org> --- gdbstub/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 565f6b33a9..6023c80d25 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -1343,8 +1343,8 @@ static void handle_read_all_regs(GArray *params, void *user_ctx) len += gdb_read_register(gdbserver_state.g_cpu, gdbserver_state.mem_buf, reg_id); + g_assert(len == gdbserver_state.mem_buf->len); } - g_assert(len == gdbserver_state.mem_buf->len); gdb_memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, len); gdb_put_strbuf(); From b2654598b3330aaa58ab0cec2114843bfa96ddaa Mon Sep 17 00:00:00 2001 From: Dominik 'Disconnect3d' Czarnota Date: Tue, 3 Jun 2025 12:02:03 +0100 Subject: [PATCH 10/11] gdbstub: Implement qGDBServerVersion packet MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds support for the `qGDBServerVersion` packet to the qemu gdbstub which could be used by clients to detect the QEMU version (and, e.g., use a workaround for known bugs). This packet is not documented/standarized by GDB but it was implemented by LLDB gdbstub [0] and is helpful for projects like Pwndbg [1]. This has been implemented by Patryk, who I included in Co-authored-by and who asked me to send the patch. [0] https://lldb.llvm.org/resources/lldbgdbremote.html#qgdbserverversion [1] https://github.com/pwndbg/pwndbg/issues/2648 Co-authored-by: Patryk 'patryk4815' Sondej Signed-off-by: Dominik 'Disconnect3d' Czarnota Message-Id: <20250403191340.53343-1-dominik.b.czarnota@gmail.com> [AJB: fix include, checkpatch linewrap] Signed-off-by: Alex Bennée Message-ID: <20250603110204.838117-17-alex.bennee@linaro.org> --- gdbstub/gdbstub.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 6023c80d25..def0b7e877 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -28,6 +28,7 @@ #include "qemu/cutils.h" #include "qemu/module.h" #include "qemu/error-report.h" +#include "qemu/target-info.h" #include "trace.h" #include "exec/gdbstub.h" #include "gdbstub/commands.h" @@ -1597,6 +1598,18 @@ static void handle_query_threads(GArray *params, void *user_ctx) gdbserver_state.query_cpu = gdb_next_attached_cpu(gdbserver_state.query_cpu); } +static void handle_query_gdb_server_version(GArray *params, void *user_ctx) +{ +#if defined(CONFIG_USER_ONLY) + g_string_printf(gdbserver_state.str_buf, "name:qemu-%s;version:%s;", + target_name(), QEMU_VERSION); +#else + g_string_printf(gdbserver_state.str_buf, "name:qemu-system-%s;version:%s;", + target_name(), QEMU_VERSION); +#endif + gdb_put_strbuf(); +} + static void handle_query_first_threads(GArray *params, void *user_ctx) { gdbserver_state.query_cpu = gdb_first_attached_cpu(); @@ -1842,6 +1855,10 @@ static const GdbCmdParseEntry gdb_gen_query_table[] = { .handler = handle_query_threads, .cmd = "sThreadInfo", }, + { + .handler = handle_query_gdb_server_version, + .cmd = "GDBServerVersion", + }, { .handler = handle_query_first_threads, .cmd = "fThreadInfo", From 63070ce368e1a2d430b9022a9db46f1817628efc Mon Sep 17 00:00:00 2001 From: Manos Pitsidianakis Date: Tue, 3 Jun 2025 12:02:04 +0100 Subject: [PATCH 11/11] gdbstub: update aarch64-core.xml MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update aarch64-core.xml to include field definitions for PSTATE, which in gdb is modelled in the cpsr (current program status register) pseudo-register, named after the actual cpsr register in armv7. Defining the fields layout of the register allows easy inspection of for example, the current exception level (EL): For example. Before booting a Linux guest, EL=2, but after booting and Ctrl-C'ing in gdb, we get EL=0: (gdb) info registers $cpsr cpsr 0x20402009 [ SP EL=2 BTYPE=0 PAN C ] (gdb) cont Continuing. ^C Thread 2 received signal SIGINT, Interrupt. 0x0000ffffaaff286c in ?? () (gdb) info registers $cpsr cpsr 0x20001000 [ EL=0 BTYPE=0 SSBS C ] The aarch64-core.xml has been updated to match exactly the version retrieved from upstream gdb, retrieved in 2025-05-19 from HEAD commit 9f4dc0b137c86f6ff2098cb1ab69442c69d6023d. Link: https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gdb/features/aarch64-core.xml;h=b8046510b9a085d30463d37b3ecc8d435f5fb7a4;hb=HEAD Signed-off-by: Manos Pitsidianakis Message-Id: <20250519-gdbstub-aarch64-pstate-xml-v1-1-b4dbe87fe7c6@linaro.org> [AJB: expanded upstream link] Signed-off-by: Alex Bennée Message-ID: <20250603110204.838117-18-alex.bennee@linaro.org> --- gdb-xml/aarch64-core.xml | 52 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/gdb-xml/aarch64-core.xml b/gdb-xml/aarch64-core.xml index e1e9dc3f91..b8046510b9 100644 --- a/gdb-xml/aarch64-core.xml +++ b/gdb-xml/aarch64-core.xml @@ -1,5 +1,5 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +