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Bring TLB / PageSize handling in line with real hardware behaviour.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2341 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-01-21 03:12:25 +00:00
parent 8e71621f78
commit bc814401c2
2 changed files with 5 additions and 25 deletions
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8
target-mips/op_helper.c
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@ -387,16 +387,11 @@ static void mips_tlb_flush_extra (CPUState *env, int first)
static void fill_tlb (int idx)
{
tlb_t *tlb;
int size;
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
tlb = &env->tlb[idx];
tlb->VPN = env->CP0_EntryHi & (int32_t)0xFFFFE000;
tlb->ASID = env->CP0_EntryHi & 0xFF;
size = env->CP0_PageMask >> 13;
size = 4 * (size + 1);
tlb->end = tlb->VPN + (1 << (8 + size));
tlb->end2 = tlb->end + (1 << (8 + size));
tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
@ -467,7 +462,6 @@ void do_tlbr (void)
{
tlb_t *tlb;
uint8_t ASID;
int size;
ASID = env->CP0_EntryHi & 0xFF;
tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
@ -479,8 +473,6 @@ void do_tlbr (void)
mips_tlb_flush_extra(env, MIPS_TLB_NB);
env->CP0_EntryHi = tlb->VPN | tlb->ASID;
size = (tlb->end - tlb->VPN) >> 12;
env->CP0_PageMask = (size - 1) << 13;
env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
(tlb->C0 << 3) | (tlb->PFN[0] >> 6);
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |