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target/riscv/vector_helper.c: skip set tail when vta is zero
The function is a no-op if 'vta' is zero but we're still doing a lot of
stuff in this function regardless. vext_set_elems_1s() will ignore every
single time (since vta is zero) and we just wasted time.
Skip it altogether in this case. Aside from the code simplification
there's a noticeable emulation performance gain by doing it. For a
regular C binary that does a vectors operation like this:
=======
#define SZ 10000000
int main ()
{
int *a = malloc (SZ * sizeof (int));
int *b = malloc (SZ * sizeof (int));
int *c = malloc (SZ * sizeof (int));
for (int i = 0; i < SZ; i++)
c[i] = a[i] + b[i];
return c[SZ - 1];
}
=======
Emulating it with qemu-riscv64 and RVV takes ~0.3 sec:
$ time ~/work/qemu/build/qemu-riscv64 \
-cpu rv64,debug=false,vext_spec=v1.0,v=true,vlen=128 ./foo.out
real 0m0.303s
user 0m0.281s
sys 0m0.023s
With this skip we take ~0.275 sec:
$ time ~/work/qemu/build/qemu-riscv64 \
-cpu rv64,debug=false,vext_spec=v1.0,v=true,vlen=128 ./foo.out
real 0m0.274s
user 0m0.252s
sys 0m0.019s
This performance gain adds up fast when executing heavy benchmarks like
SPEC.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230427205708.246679-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
parent
fdd0df5340
commit
bc0ec52eb2
1 changed files with 8 additions and 3 deletions
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@ -268,12 +268,17 @@ static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
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void *vd, uint32_t desc, uint32_t nf,
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uint32_t esz, uint32_t max_elems)
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{
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uint32_t total_elems = vext_get_total_elems(env, desc, esz);
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uint32_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
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uint32_t total_elems, vlenb, registers_used;
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uint32_t vta = vext_vta(desc);
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uint32_t registers_used;
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int k;
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if (vta == 0) {
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return;
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}
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total_elems = vext_get_total_elems(env, desc, esz);
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vlenb = riscv_cpu_cfg(env)->vlen >> 3;
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for (k = 0; k < nf; ++k) {
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vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz,
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(k * max_elems + max_elems) * esz);
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