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Parse SDR1 on mtspr instead of at translate time

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On ppc machines with hash table MMUs, the special purpose register SDR1
contains both the base address of the encoded size (hashed) page tables.

At present, we interpret the SDR1 value within the address translation
path.  But because the encodings of the size for 32-bit and 64-bit are
different this makes for a confusing branch on the MMU type with a bunch
of curly shifts and masks in the middle of the translate path.

This patch cleans things up by moving the interpretation on SDR1 into the
helper function handling the write to the register.  This leaves a simple
pre-sanitized base address and mask for the hash table in the CPUState
structure which is easier to work with in the translation path.

This makes the translation path more readable.  It addresses the FIXME
comment currently in the mtsdr1 helper, by validating the SDR1 value during
interpretation.  Finally it opens the way for emulating a pSeries-style
partition where the hash table used for translation is not mapped into
the guests's RAM.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
David Gibson 2011-04-01 15:15:15 +11:00 • committed by Alexander Graf
parent 8500e3a912
commit bb593904c1
7 changed files with 63 additions and 47 deletions
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11
target-ppc/cpu.h
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@ -359,6 +359,14 @@ union ppc_tlb_t {
};
#endif
#define SDR_32_HTABORG 0xFFFF0000UL
#define SDR_32_HTABMASK 0x000001FFUL
#if defined(TARGET_PPC64)
#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
#define SDR_64_HTABSIZE 0x000000000000001FULL
#endif /* defined(TARGET_PPC64 */
typedef struct ppc_slb_t ppc_slb_t;
struct ppc_slb_t {
uint64_t esid;
@ -642,7 +650,8 @@ struct CPUPPCState {
int slb_nr;
#endif
/* segment registers */
target_ulong sdr1;
target_phys_addr_t htab_base;
target_phys_addr_t htab_mask;
target_ulong sr[32];
/* BATs */
int nb_BATs;