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target/hppa: Implement PA2.0 instructions
hw/hppa: Map astro chip 64-bit I/O mem hw/hppa: Turn on 64-bit cpu for C3700 -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmVJqDEdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8n5Qf/R15CvXGMgjDJjoV2 ILMFM+Rpg17SR2yu060sEZ01R3iHdobeCcDB184K0RI9JLrpcBFar+PeF023o9fn O9MnfIyL6/ggzaeIpQ9AD2uT0HJMU9hLFoyQqQvnhDHHcT34raL2+Zkrkb2vvauH XET7awXN9xYCnY4ALrfcapzlrHqI77ahz0vReUWPxk7eGY2ez8dEOiFW2WLBmuMx mAFAMrFQhq66GjoMDl8JiGHD/KBJQ9X4eUAEotS27lTCOYU0ryA6dWBGqBSTWCUa smpxkeGQKOew+717HV1H4FdCRYG1Rgm7yFN423JULeew+T7DHvfe0K55vMIulx5I g3oVZA== =dxC7 -----END PGP SIGNATURE----- Merge tag 'pull-pa-20231106' of https://gitlab.com/rth7680/qemu into staging target/hppa: Implement PA2.0 instructions hw/hppa: Map astro chip 64-bit I/O mem hw/hppa: Turn on 64-bit cpu for C3700 # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmVJqDEdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8n5Qf/R15CvXGMgjDJjoV2 # ILMFM+Rpg17SR2yu060sEZ01R3iHdobeCcDB184K0RI9JLrpcBFar+PeF023o9fn # O9MnfIyL6/ggzaeIpQ9AD2uT0HJMU9hLFoyQqQvnhDHHcT34raL2+Zkrkb2vvauH # XET7awXN9xYCnY4ALrfcapzlrHqI77ahz0vReUWPxk7eGY2ez8dEOiFW2WLBmuMx # mAFAMrFQhq66GjoMDl8JiGHD/KBJQ9X4eUAEotS27lTCOYU0ryA6dWBGqBSTWCUa # smpxkeGQKOew+717HV1H4FdCRYG1Rgm7yFN423JULeew+T7DHvfe0K55vMIulx5I # g3oVZA== # =dxC7 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 11:00:01 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-pa-20231106' of https://gitlab.com/rth7680/qemu: (85 commits) hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only hw/hppa: Turn on 64-bit CPU for C3700 machine hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region target/hppa: Improve interrupt logging target/hppa: Update IIAOQ, IIASQ for pa2.0 target/hppa: Create raise_exception_with_ior target/hppa: Add unwind_breg to CPUHPPAState target/hppa: Clear upper bits in mtctl for pa1.x target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system target/hppa: Add pa2.0 cpu local tlb flushes target/hppa: Implement pa2.0 data prefetch instructions linux-user/hppa: Drop EXCP_DUMP from handled exceptions hw/hppa: Translate phys addresses for the cpu include/hw/elf: Remove truncating signed casts target/hppa: Return zero for r0 from load_gpr target/hppa: Precompute zero into DisasContext target/hppa: Fix interruption based on default PSW target/hppa: Implement PERMH target/hppa: Implement MIXH, MIXW ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
commit
bb541a7068
22 changed files with 2576 additions and 1442 deletions
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@ -147,12 +147,10 @@ void cpu_loop(CPUHPPAState *env)
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force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, env->iaoq_f);
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break;
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case EXCP_ILL:
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EXCP_DUMP(env, "qemu: EXCP_ILL exception %#x\n", trapnr);
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f);
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break;
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case EXCP_PRIV_OPR:
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/* check for glibc ABORT_INSTRUCTION "iitlbp %r0,(%sr0, %r0)" */
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EXCP_DUMP(env, "qemu: EXCP_PRIV_OPR exception %#x\n", trapnr);
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if (env->cr[CR_IIR] == 0x04000000) {
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f);
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} else {
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@ -160,7 +158,6 @@ void cpu_loop(CPUHPPAState *env)
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}
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break;
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case EXCP_PRIV_REG:
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EXCP_DUMP(env, "qemu: EXCP_PRIV_REG exception %#x\n", trapnr);
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVREG, env->iaoq_f);
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break;
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case EXCP_OVERFLOW:
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@ -173,7 +170,6 @@ void cpu_loop(CPUHPPAState *env)
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force_sig_fault(TARGET_SIGFPE, 0, env->iaoq_f);
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break;
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case EXCP_BREAK:
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EXCP_DUMP(env, "qemu: EXCP_BREAK exception %#x\n", trapnr);
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f & ~3);
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break;
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case EXCP_DEBUG:
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@ -86,7 +86,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUArchState *env)
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static void restore_sigcontext(CPUArchState *env, struct target_sigcontext *sc)
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{
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target_ulong psw;
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abi_ulong psw;
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int i;
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__get_user(psw, &sc->sc_gr[0]);
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@ -150,10 +150,10 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
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haddr = ka->_sa_handler;
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if (haddr & 2) {
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/* Function descriptor. */
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target_ulong *fdesc, dest;
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abi_ptr *fdesc, dest;
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haddr &= -4;
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fdesc = lock_user(VERIFY_READ, haddr, 2 * sizeof(target_ulong), 1);
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fdesc = lock_user(VERIFY_READ, haddr, 2 * sizeof(abi_ptr), 1);
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if (!fdesc) {
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goto give_sigsegv;
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}
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@ -9,6 +9,6 @@
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#define HPPA_TARGET_ELF_H
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static inline const char *cpu_get_model(uint32_t eflags)
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{
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return "any";
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return "hppa";
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}
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#endif
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