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target/riscv: Add V extension state description

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In the case of supporting V extension, add V extension description
to vmstate_riscv_cpu.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-6-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Yifei Jiang 2020-10-26 19:55:29 +08:00 • committed by Alistair Francis
parent 35e07821ff
commit bb02edcd86
1 changed files with 25 additions and 0 deletions
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25
target/riscv/machine.c
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@ -76,6 +76,30 @@ static bool hyper_needed(void *opaque)
return riscv_has_ext(env, RVH); return riscv_has_ext(env, RVH);
} }
static bool vector_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
return riscv_has_ext(env, RVV);
}
static const VMStateDescription vmstate_vector = {
.name = "cpu/vector",
.version_id = 1,
.minimum_version_id = 1,
.needed = vector_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
VMSTATE_UINTTL(env.vxrm, RISCVCPU),
VMSTATE_UINTTL(env.vxsat, RISCVCPU),
VMSTATE_UINTTL(env.vl, RISCVCPU),
VMSTATE_UINTTL(env.vstart, RISCVCPU),
VMSTATE_UINTTL(env.vtype, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_hyper = { static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper", .name = "cpu/hyper",
.version_id = 1, .version_id = 1,
@ -166,6 +190,7 @@ const VMStateDescription vmstate_riscv_cpu = {
.subsections = (const VMStateDescription * []) { .subsections = (const VMStateDescription * []) {
&vmstate_pmp, &vmstate_pmp,
&vmstate_hyper, &vmstate_hyper,
&vmstate_vector,
NULL NULL
} }
}; };