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target/ppc: Split off BookE handling from ppc_jumbo_xlate()
Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to reduce ppc_jumbo_xlate() further. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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1 changed files with 96 additions and 50 deletions
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@ -1117,21 +1117,9 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
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MMUAccessType access_type, int type,
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MMUAccessType access_type, int type,
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int mmu_idx)
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int mmu_idx)
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{
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{
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bool real_mode;
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bool real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
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: !FIELD_EX64(env->msr, MSR, DR);
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if (env->mmu_model == POWERPC_MMU_BOOKE) {
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if (real_mode) {
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return mmubooke_get_physical_address(env, &ctx->raddr, &ctx->prot,
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eaddr, access_type);
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} else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
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return mmubooke206_get_physical_address(env, &ctx->raddr, &ctx->prot,
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eaddr, access_type, mmu_idx);
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}
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real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
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: !FIELD_EX64(env->msr, MSR, DR);
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if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
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env->mmu_model == POWERPC_MMU_SOFT_4xx ||
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env->mmu_model == POWERPC_MMU_REAL)) {
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ctx->raddr = eaddr;
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ctx->raddr = eaddr;
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ctx->prot = PAGE_RWX;
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ctx->prot = PAGE_RWX;
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return 0;
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return 0;
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@ -1205,6 +1193,93 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
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env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
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env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
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}
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}
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static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
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MMUAccessType access_type,
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hwaddr *raddrp, int *psizep, int *protp,
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int mmu_idx, bool guest_visible)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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hwaddr raddr;
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int prot, ret;
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if (env->mmu_model == POWERPC_MMU_BOOKE206) {
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ret = mmubooke206_get_physical_address(env, &raddr, &prot, eaddr,
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access_type, mmu_idx);
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} else {
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ret = mmubooke_get_physical_address(env, &raddr, &prot, eaddr,
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access_type);
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}
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if (ret == 0) {
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*raddrp = raddr;
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*protp = prot;
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*psizep = TARGET_PAGE_BITS;
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return true;
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} else if (!guest_visible) {
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return false;
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}
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log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
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if (access_type == MMU_INST_FETCH) {
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switch (ret) {
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case -1:
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/* No matches in page tables or TLB */
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switch (env->mmu_model) {
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case POWERPC_MMU_BOOKE206:
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booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
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/* fall through */
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case POWERPC_MMU_BOOKE:
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cs->exception_index = POWERPC_EXCP_ITLB;
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env->error_code = 0;
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env->spr[SPR_BOOKE_DEAR] = eaddr;
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env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
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break;
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default:
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g_assert_not_reached();
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}
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break;
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case -2:
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/* Access rights violation */
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cs->exception_index = POWERPC_EXCP_ISI;
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env->error_code = 0;
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break;
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case -3:
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/* No execute protection violation */
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cs->exception_index = POWERPC_EXCP_ISI;
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env->spr[SPR_BOOKE_ESR] = 0;
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env->error_code = 0;
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break;
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}
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} else {
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switch (ret) {
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case -1:
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/* No matches in page tables or TLB */
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switch (env->mmu_model) {
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case POWERPC_MMU_BOOKE206:
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booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
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/* fall through */
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case POWERPC_MMU_BOOKE:
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cs->exception_index = POWERPC_EXCP_DTLB;
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env->error_code = 0;
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env->spr[SPR_BOOKE_DEAR] = eaddr;
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env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
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break;
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default:
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g_assert_not_reached();
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}
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break;
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case -2:
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/* Access rights violation */
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cs->exception_index = POWERPC_EXCP_DSI;
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env->error_code = 0;
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env->spr[SPR_BOOKE_DEAR] = eaddr;
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env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
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break;
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}
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}
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return false;
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}
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/* Perform address translation */
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/* Perform address translation */
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/* TODO: Split this by mmu_model. */
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/* TODO: Split this by mmu_model. */
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static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
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static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
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@ -1257,15 +1332,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
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env->spr[SPR_40x_DEAR] = eaddr;
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env->spr[SPR_40x_DEAR] = eaddr;
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env->spr[SPR_40x_ESR] = 0x00000000;
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env->spr[SPR_40x_ESR] = 0x00000000;
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break;
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break;
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case POWERPC_MMU_BOOKE206:
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booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
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/* fall through */
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case POWERPC_MMU_BOOKE:
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cs->exception_index = POWERPC_EXCP_ITLB;
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env->error_code = 0;
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env->spr[SPR_BOOKE_DEAR] = eaddr;
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env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
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break;
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case POWERPC_MMU_REAL:
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case POWERPC_MMU_REAL:
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cpu_abort(cs, "PowerPC in real mode should never raise "
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cpu_abort(cs, "PowerPC in real mode should never raise "
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"any MMU exceptions\n");
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"any MMU exceptions\n");
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@ -1276,23 +1342,12 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
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case -2:
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case -2:
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/* Access rights violation */
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/* Access rights violation */
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cs->exception_index = POWERPC_EXCP_ISI;
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cs->exception_index = POWERPC_EXCP_ISI;
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if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
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env->error_code = 0x08000000;
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(env->mmu_model == POWERPC_MMU_BOOKE206)) {
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env->error_code = 0;
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} else {
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env->error_code = 0x08000000;
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}
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break;
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break;
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case -3:
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case -3:
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/* No execute protection violation */
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/* No execute protection violation */
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if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
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(env->mmu_model == POWERPC_MMU_BOOKE206)) {
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env->spr[SPR_BOOKE_ESR] = 0x00000000;
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env->error_code = 0;
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} else {
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env->error_code = 0x10000000;
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}
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cs->exception_index = POWERPC_EXCP_ISI;
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cs->exception_index = POWERPC_EXCP_ISI;
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env->error_code = 0x10000000;
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break;
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break;
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case -4:
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case -4:
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/* Direct store exception */
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/* Direct store exception */
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@ -1333,15 +1388,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
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env->spr[SPR_40x_ESR] = 0x00000000;
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env->spr[SPR_40x_ESR] = 0x00000000;
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}
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}
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break;
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break;
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case POWERPC_MMU_BOOKE206:
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booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
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/* fall through */
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case POWERPC_MMU_BOOKE:
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cs->exception_index = POWERPC_EXCP_DTLB;
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env->error_code = 0;
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env->spr[SPR_BOOKE_DEAR] = eaddr;
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env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
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break;
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case POWERPC_MMU_REAL:
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case POWERPC_MMU_REAL:
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cpu_abort(cs, "PowerPC in real mode should never raise "
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cpu_abort(cs, "PowerPC in real mode should never raise "
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"any MMU exceptions\n");
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"any MMU exceptions\n");
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@ -1358,10 +1404,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
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if (access_type == MMU_DATA_STORE) {
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if (access_type == MMU_DATA_STORE) {
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env->spr[SPR_40x_ESR] |= 0x00800000;
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env->spr[SPR_40x_ESR] |= 0x00800000;
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}
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}
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} else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
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(env->mmu_model == POWERPC_MMU_BOOKE206)) {
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env->spr[SPR_BOOKE_DEAR] = eaddr;
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env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
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} else {
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} else {
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env->spr[SPR_DAR] = eaddr;
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env->spr[SPR_DAR] = eaddr;
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if (access_type == MMU_DATA_STORE) {
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if (access_type == MMU_DATA_STORE) {
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@ -1440,6 +1482,10 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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case POWERPC_MMU_32B:
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case POWERPC_MMU_32B:
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return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp,
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return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp,
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psizep, protp, mmu_idx, guest_visible);
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psizep, protp, mmu_idx, guest_visible);
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case POWERPC_MMU_BOOKE:
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case POWERPC_MMU_BOOKE206:
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return ppc_booke_xlate(cpu, eaddr, access_type, raddrp,
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psizep, protp, mmu_idx, guest_visible);
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case POWERPC_MMU_MPC8xx:
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case POWERPC_MMU_MPC8xx:
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cpu_abort(env_cpu(&cpu->env), "MPC8xx MMU model is not implemented\n");
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cpu_abort(env_cpu(&cpu->env), "MPC8xx MMU model is not implemented\n");
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default:
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default:
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