mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 00:03:54 -06:00
hw/arm: Mark Allwinner Technology devices as little-endian
These devices are only used by the ARM targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250212113938.38692-2-philmd@linaro.org>
This commit is contained in:
parent
e87c93df11
commit
ba26f14777
22 changed files with 31 additions and 31 deletions
|
@ -158,7 +158,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
|
||||||
/* FIXME use a qdev chardev prop instead of serial_hd() */
|
/* FIXME use a qdev chardev prop instead of serial_hd() */
|
||||||
serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
|
serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
|
||||||
qdev_get_gpio_in(dev, 1),
|
qdev_get_gpio_in(dev, 1),
|
||||||
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
|
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
|
||||||
|
|
||||||
for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
|
for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
|
||||||
g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
|
g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
|
||||||
|
|
|
@ -408,19 +408,19 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
|
||||||
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
|
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
|
||||||
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
|
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
|
||||||
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
|
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
|
||||||
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
|
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
|
||||||
/* UART1 */
|
/* UART1 */
|
||||||
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
|
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
|
||||||
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
|
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
|
||||||
115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
|
115200, serial_hd(1), DEVICE_LITTLE_ENDIAN);
|
||||||
/* UART2 */
|
/* UART2 */
|
||||||
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
|
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
|
||||||
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
|
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
|
||||||
115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
|
115200, serial_hd(2), DEVICE_LITTLE_ENDIAN);
|
||||||
/* UART3 */
|
/* UART3 */
|
||||||
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
|
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
|
||||||
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
|
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
|
||||||
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
|
115200, serial_hd(3), DEVICE_LITTLE_ENDIAN);
|
||||||
|
|
||||||
/* DRAMC */
|
/* DRAMC */
|
||||||
sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
|
sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
|
||||||
|
|
|
@ -492,7 +492,7 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp)
|
||||||
|
|
||||||
serial_mm_init(get_system_memory(), addr, 2,
|
serial_mm_init(get_system_memory(), addr, 2,
|
||||||
qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]),
|
qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]),
|
||||||
115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
|
115200, serial_hd(i), DEVICE_LITTLE_ENDIAN);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* I2C */
|
/* I2C */
|
||||||
|
|
|
@ -407,7 +407,7 @@ static const MemoryRegionOps allwinner_i2c_ops = {
|
||||||
.write = allwinner_i2c_write,
|
.write = allwinner_i2c_write,
|
||||||
.valid.min_access_size = 1,
|
.valid.min_access_size = 1,
|
||||||
.valid.max_access_size = 4,
|
.valid.max_access_size = 4,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const VMStateDescription allwinner_i2c_vmstate = {
|
static const VMStateDescription allwinner_i2c_vmstate = {
|
||||||
|
|
|
@ -135,7 +135,7 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
|
||||||
static const MemoryRegionOps aw_a10_pic_ops = {
|
static const MemoryRegionOps aw_a10_pic_ops = {
|
||||||
.read = aw_a10_pic_read,
|
.read = aw_a10_pic_read,
|
||||||
.write = aw_a10_pic_write,
|
.write = aw_a10_pic_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const VMStateDescription vmstate_aw_a10_pic = {
|
static const VMStateDescription vmstate_aw_a10_pic = {
|
||||||
|
|
|
@ -147,7 +147,7 @@ static void allwinner_a10_ccm_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_a10_ccm_ops = {
|
static const MemoryRegionOps allwinner_a10_ccm_ops = {
|
||||||
.read = allwinner_a10_ccm_read,
|
.read = allwinner_a10_ccm_read,
|
||||||
.write = allwinner_a10_ccm_write,
|
.write = allwinner_a10_ccm_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -114,7 +114,7 @@ static void allwinner_a10_dramc_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_a10_dramc_ops = {
|
static const MemoryRegionOps allwinner_a10_dramc_ops = {
|
||||||
.read = allwinner_a10_dramc_read,
|
.read = allwinner_a10_dramc_read,
|
||||||
.write = allwinner_a10_dramc_write,
|
.write = allwinner_a10_dramc_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -217,7 +217,7 @@ static void allwinner_cpucfg_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_cpucfg_ops = {
|
static const MemoryRegionOps allwinner_cpucfg_ops = {
|
||||||
.read = allwinner_cpucfg_read,
|
.read = allwinner_cpucfg_read,
|
||||||
.write = allwinner_cpucfg_write,
|
.write = allwinner_cpucfg_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -155,7 +155,7 @@ static void allwinner_h3_ccu_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_h3_ccu_ops = {
|
static const MemoryRegionOps allwinner_h3_ccu_ops = {
|
||||||
.read = allwinner_h3_ccu_read,
|
.read = allwinner_h3_ccu_read,
|
||||||
.write = allwinner_h3_ccu_write,
|
.write = allwinner_h3_ccu_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -219,7 +219,7 @@ static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_h3_dramcom_ops = {
|
static const MemoryRegionOps allwinner_h3_dramcom_ops = {
|
||||||
.read = allwinner_h3_dramcom_read,
|
.read = allwinner_h3_dramcom_read,
|
||||||
.write = allwinner_h3_dramcom_write,
|
.write = allwinner_h3_dramcom_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
@ -230,7 +230,7 @@ static const MemoryRegionOps allwinner_h3_dramcom_ops = {
|
||||||
static const MemoryRegionOps allwinner_h3_dramctl_ops = {
|
static const MemoryRegionOps allwinner_h3_dramctl_ops = {
|
||||||
.read = allwinner_h3_dramctl_read,
|
.read = allwinner_h3_dramctl_read,
|
||||||
.write = allwinner_h3_dramctl_write,
|
.write = allwinner_h3_dramctl_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
@ -241,7 +241,7 @@ static const MemoryRegionOps allwinner_h3_dramctl_ops = {
|
||||||
static const MemoryRegionOps allwinner_h3_dramphy_ops = {
|
static const MemoryRegionOps allwinner_h3_dramphy_ops = {
|
||||||
.read = allwinner_h3_dramphy_read,
|
.read = allwinner_h3_dramphy_read,
|
||||||
.write = allwinner_h3_dramphy_write,
|
.write = allwinner_h3_dramphy_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -78,7 +78,7 @@ static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
|
static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
|
||||||
.read = allwinner_h3_sysctrl_read,
|
.read = allwinner_h3_sysctrl_read,
|
||||||
.write = allwinner_h3_sysctrl_write,
|
.write = allwinner_h3_sysctrl_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -129,7 +129,7 @@ static void allwinner_r40_ccu_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_r40_ccu_ops = {
|
static const MemoryRegionOps allwinner_r40_ccu_ops = {
|
||||||
.read = allwinner_r40_ccu_read,
|
.read = allwinner_r40_ccu_read,
|
||||||
.write = allwinner_r40_ccu_write,
|
.write = allwinner_r40_ccu_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -297,7 +297,7 @@ static void allwinner_r40_dramphy_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_r40_dramcom_ops = {
|
static const MemoryRegionOps allwinner_r40_dramcom_ops = {
|
||||||
.read = allwinner_r40_dramcom_read,
|
.read = allwinner_r40_dramcom_read,
|
||||||
.write = allwinner_r40_dramcom_write,
|
.write = allwinner_r40_dramcom_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
@ -308,7 +308,7 @@ static const MemoryRegionOps allwinner_r40_dramcom_ops = {
|
||||||
static const MemoryRegionOps allwinner_r40_dramctl_ops = {
|
static const MemoryRegionOps allwinner_r40_dramctl_ops = {
|
||||||
.read = allwinner_r40_dramctl_read,
|
.read = allwinner_r40_dramctl_read,
|
||||||
.write = allwinner_r40_dramctl_write,
|
.write = allwinner_r40_dramctl_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
@ -319,7 +319,7 @@ static const MemoryRegionOps allwinner_r40_dramctl_ops = {
|
||||||
static const MemoryRegionOps allwinner_r40_dramphy_ops = {
|
static const MemoryRegionOps allwinner_r40_dramphy_ops = {
|
||||||
.read = allwinner_r40_dramphy_read,
|
.read = allwinner_r40_dramphy_read,
|
||||||
.write = allwinner_r40_dramphy_write,
|
.write = allwinner_r40_dramphy_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
@ -358,7 +358,7 @@ static void allwinner_r40_detect_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_r40_detect_ops = {
|
static const MemoryRegionOps allwinner_r40_detect_ops = {
|
||||||
.read = allwinner_r40_detect_read,
|
.read = allwinner_r40_detect_read,
|
||||||
.write = allwinner_r40_detect_write,
|
.write = allwinner_r40_detect_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
@ -393,7 +393,7 @@ static uint64_t allwinner_r40_dualrank_detect_read(void *opaque, hwaddr offset,
|
||||||
|
|
||||||
static const MemoryRegionOps allwinner_r40_dualrank_detect_ops = {
|
static const MemoryRegionOps allwinner_r40_dualrank_detect_ops = {
|
||||||
.read = allwinner_r40_dualrank_detect_read,
|
.read = allwinner_r40_dualrank_detect_read,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -99,7 +99,7 @@ static void allwinner_sid_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_sid_ops = {
|
static const MemoryRegionOps allwinner_sid_ops = {
|
||||||
.read = allwinner_sid_read,
|
.read = allwinner_sid_read,
|
||||||
.write = allwinner_sid_write,
|
.write = allwinner_sid_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -104,7 +104,7 @@ static void allwinner_sramc_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_sramc_ops = {
|
static const MemoryRegionOps allwinner_sramc_ops = {
|
||||||
.read = allwinner_sramc_read,
|
.read = allwinner_sramc_read,
|
||||||
.write = allwinner_sramc_write,
|
.write = allwinner_sramc_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -784,7 +784,7 @@ static void allwinner_sun8i_emac_set_link(NetClientState *nc)
|
||||||
static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = {
|
static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = {
|
||||||
.read = allwinner_sun8i_emac_read,
|
.read = allwinner_sun8i_emac_read,
|
||||||
.write = allwinner_sun8i_emac_write,
|
.write = allwinner_sun8i_emac_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -421,7 +421,7 @@ static void aw_emac_set_link(NetClientState *nc)
|
||||||
static const MemoryRegionOps aw_emac_mem_ops = {
|
static const MemoryRegionOps aw_emac_mem_ops = {
|
||||||
.read = aw_emac_read,
|
.read = aw_emac_read,
|
||||||
.write = aw_emac_write,
|
.write = aw_emac_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -259,7 +259,7 @@ static void allwinner_rtc_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_rtc_ops = {
|
static const MemoryRegionOps allwinner_rtc_ops = {
|
||||||
.read = allwinner_rtc_read,
|
.read = allwinner_rtc_read,
|
||||||
.write = allwinner_rtc_write,
|
.write = allwinner_rtc_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -761,7 +761,7 @@ static void allwinner_sdhost_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_sdhost_ops = {
|
static const MemoryRegionOps allwinner_sdhost_ops = {
|
||||||
.read = allwinner_sdhost_read,
|
.read = allwinner_sdhost_read,
|
||||||
.write = allwinner_sdhost_write,
|
.write = allwinner_sdhost_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
|
@ -502,7 +502,7 @@ static const MemoryRegionOps allwinner_a10_spi_ops = {
|
||||||
.write = allwinner_a10_spi_write,
|
.write = allwinner_a10_spi_write,
|
||||||
.valid.min_access_size = 1,
|
.valid.min_access_size = 1,
|
||||||
.valid.max_access_size = 4,
|
.valid.max_access_size = 4,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const VMStateDescription allwinner_a10_spi_vmstate = {
|
static const VMStateDescription allwinner_a10_spi_vmstate = {
|
||||||
|
|
|
@ -185,7 +185,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
|
||||||
static const MemoryRegionOps a10_pit_ops = {
|
static const MemoryRegionOps a10_pit_ops = {
|
||||||
.read = a10_pit_read,
|
.read = a10_pit_read,
|
||||||
.write = a10_pit_write,
|
.write = a10_pit_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const Property a10_pit_properties[] = {
|
static const Property a10_pit_properties[] = {
|
||||||
|
|
|
@ -275,7 +275,7 @@ static void allwinner_wdt_write(void *opaque, hwaddr offset,
|
||||||
static const MemoryRegionOps allwinner_wdt_ops = {
|
static const MemoryRegionOps allwinner_wdt_ops = {
|
||||||
.read = allwinner_wdt_read,
|
.read = allwinner_wdt_read,
|
||||||
.write = allwinner_wdt_write,
|
.write = allwinner_wdt_write,
|
||||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
.valid = {
|
.valid = {
|
||||||
.min_access_size = 4,
|
.min_access_size = 4,
|
||||||
.max_access_size = 4,
|
.max_access_size = 4,
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue