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target/arm: Reorganize ARMMMUIdx

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Prepare for, but do not yet implement, the EL2&0 regime.
This involves adding the new MMUIdx enumerators and adjusting
some of the MMUIdx related predicates to match.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-07 14:04:24 +00:00 • committed by Peter Maydell
parent 25568316b2
commit b9f6033c1a
5 changed files with 152 additions and 86 deletions
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66
target/arm/helper.c
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@ -8707,9 +8707,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
#endif /* !CONFIG_USER_ONLY */
/* Return the exception level which controls this address translation regime */
static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_E20_0:
case ARMMMUIdx_E20_2:
case ARMMMUIdx_Stage2:
case ARMMMUIdx_E2:
return 2;
@ -8720,6 +8722,8 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
case ARMMMUIdx_SE10_1:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_Stage1_E1:
case ARMMMUIdx_E10_0:
case ARMMMUIdx_E10_1:
case ARMMMUIdx_MPrivNegPri:
case ARMMMUIdx_MUserNegPri:
case ARMMMUIdx_MPriv:
@ -8821,10 +8825,14 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
*/
static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
{
if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) {
mmu_idx += (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_E10_0);
switch (mmu_idx) {
case ARMMMUIdx_E10_0:
return ARMMMUIdx_Stage1_E0;
case ARMMMUIdx_E10_1:
return ARMMMUIdx_Stage1_E1;
default:
return mmu_idx;
}
return mmu_idx;
}
/* Return true if the translation regime is using LPAE format page tables */
@ -8857,6 +8865,7 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_SE10_0:
case ARMMMUIdx_E20_0:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_MUser:
case ARMMMUIdx_MSUser:
@ -11282,6 +11291,31 @@ int fp_exception_el(CPUARMState *env, int cur_el)
return 0;
}
/* Return the exception level we're running at if this is our mmu_idx */
int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
{
if (mmu_idx & ARM_MMU_IDX_M) {
return mmu_idx & ARM_MMU_IDX_M_PRIV;
}
switch (mmu_idx) {
case ARMMMUIdx_E10_0:
case ARMMMUIdx_E20_0:
case ARMMMUIdx_SE10_0:
return 0;
case ARMMMUIdx_E10_1:
case ARMMMUIdx_SE10_1:
return 1;
case ARMMMUIdx_E2:
case ARMMMUIdx_E20_2:
return 2;
case ARMMMUIdx_SE3:
return 3;
default:
g_assert_not_reached();
}
}
#ifndef CONFIG_TCG
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
{
@ -11295,10 +11329,26 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
}
if (el < 2 && arm_is_secure_below_el3(env)) {
return ARMMMUIdx_SE10_0 + el;
} else {
return ARMMMUIdx_E10_0 + el;
switch (el) {
case 0:
/* TODO: ARMv8.1-VHE */
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdx_SE10_0;
}
return ARMMMUIdx_E10_0;
case 1:
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdx_SE10_1;
}
return ARMMMUIdx_E10_1;
case 2:
/* TODO: ARMv8.1-VHE */
/* TODO: ARMv8.4-SecEL2 */
return ARMMMUIdx_E2;
case 3:
return ARMMMUIdx_SE3;
default:
g_assert_not_reached();
}
}