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include/exec: Split out exec/cpu-interrupt.h
Some of these bits are actually common to all cpus; while the reset have common reservations for target-specific usage. While generic code cannot know what the target-specific usage is, common code can know what to do with the bits, e.g. single-step. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson
parent
58d00538ce
commit
b9e3bf884a
3 changed files with 71 additions and 65 deletions
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@ -21,6 +21,7 @@
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#include "exec/page-protection.h"
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#include "exec/page-protection.h"
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#include "exec/cpu-common.h"
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#include "exec/cpu-common.h"
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#include "exec/cpu-interrupt.h"
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#include "exec/memory.h"
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#include "exec/memory.h"
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#include "exec/tswap.h"
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#include "exec/tswap.h"
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#include "hw/core/cpu.h"
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#include "hw/core/cpu.h"
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@ -109,58 +110,6 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
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CPUArchState *cpu_copy(CPUArchState *env);
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CPUArchState *cpu_copy(CPUArchState *env);
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/* Flags for use in ENV->INTERRUPT_PENDING.
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The numbers assigned here are non-sequential in order to preserve
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binary compatibility with the vmstate dump. Bit 0 (0x0001) was
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previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
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the vmstate dump. */
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/* External hardware interrupt pending. This is typically used for
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interrupts from devices. */
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#define CPU_INTERRUPT_HARD 0x0002
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/* Exit the current TB. This is typically used when some system-level device
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makes some change to the memory mapping. E.g. the a20 line change. */
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#define CPU_INTERRUPT_EXITTB 0x0004
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/* Halt the CPU. */
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#define CPU_INTERRUPT_HALT 0x0020
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/* Debug event pending. */
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#define CPU_INTERRUPT_DEBUG 0x0080
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/* Reset signal. */
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#define CPU_INTERRUPT_RESET 0x0400
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/* Several target-specific external hardware interrupts. Each target/cpu.h
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should define proper names based on these defines. */
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#define CPU_INTERRUPT_TGT_EXT_0 0x0008
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#define CPU_INTERRUPT_TGT_EXT_1 0x0010
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#define CPU_INTERRUPT_TGT_EXT_2 0x0040
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#define CPU_INTERRUPT_TGT_EXT_3 0x0200
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#define CPU_INTERRUPT_TGT_EXT_4 0x1000
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/* Several target-specific internal interrupts. These differ from the
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preceding target-specific interrupts in that they are intended to
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originate from within the cpu itself, typically in response to some
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instruction being executed. These, therefore, are not masked while
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single-stepping within the debugger. */
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#define CPU_INTERRUPT_TGT_INT_0 0x0100
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#define CPU_INTERRUPT_TGT_INT_1 0x0800
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#define CPU_INTERRUPT_TGT_INT_2 0x2000
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/* First unused bit: 0x4000. */
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/* The set of all bits that should be masked when single-stepping. */
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#define CPU_INTERRUPT_SSTEP_MASK \
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(CPU_INTERRUPT_HARD \
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| CPU_INTERRUPT_TGT_EXT_0 \
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| CPU_INTERRUPT_TGT_EXT_1 \
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| CPU_INTERRUPT_TGT_EXT_2 \
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| CPU_INTERRUPT_TGT_EXT_3 \
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| CPU_INTERRUPT_TGT_EXT_4)
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#include "cpu.h"
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#include "cpu.h"
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#ifdef CONFIG_USER_ONLY
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#ifdef CONFIG_USER_ONLY
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70
include/exec/cpu-interrupt.h
Normal file
70
include/exec/cpu-interrupt.h
Normal file
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@ -0,0 +1,70 @@
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/*
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* Flags for use with cpu_interrupt()
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*
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* Copyright (c) 2003 Fabrice Bellard
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#ifndef CPU_INTERRUPT_H
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#define CPU_INTERRUPT_H
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/*
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* The numbers assigned here are non-sequential in order to preserve binary
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* compatibility with the vmstate dump. Bit 0 (0x0001) was previously used
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* for CPU_INTERRUPT_EXIT, and is cleared when loading the vmstate dump.
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*/
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/*
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* External hardware interrupt pending.
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* This is typically used for interrupts from devices.
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*/
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#define CPU_INTERRUPT_HARD 0x0002
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/*
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* Exit the current TB. This is typically used when some system-level device
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* makes some change to the memory mapping. E.g. the a20 line change.
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*/
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#define CPU_INTERRUPT_EXITTB 0x0004
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/* Halt the CPU. */
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#define CPU_INTERRUPT_HALT 0x0020
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/* Debug event pending. */
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#define CPU_INTERRUPT_DEBUG 0x0080
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/* Reset signal. */
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#define CPU_INTERRUPT_RESET 0x0400
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/*
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* Several target-specific external hardware interrupts. Each target/cpu.h
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* should define proper names based on these defines.
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*/
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#define CPU_INTERRUPT_TGT_EXT_0 0x0008
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#define CPU_INTERRUPT_TGT_EXT_1 0x0010
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#define CPU_INTERRUPT_TGT_EXT_2 0x0040
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#define CPU_INTERRUPT_TGT_EXT_3 0x0200
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#define CPU_INTERRUPT_TGT_EXT_4 0x1000
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/*
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* Several target-specific internal interrupts. These differ from the
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* preceding target-specific interrupts in that they are intended to
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* originate from within the cpu itself, typically in response to some
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* instruction being executed. These, therefore, are not masked while
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* single-stepping within the debugger.
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*/
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#define CPU_INTERRUPT_TGT_INT_0 0x0100
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#define CPU_INTERRUPT_TGT_INT_1 0x0800
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#define CPU_INTERRUPT_TGT_INT_2 0x2000
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/* First unused bit: 0x4000. */
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/* The set of all bits that should be masked when single-stepping. */
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#define CPU_INTERRUPT_SSTEP_MASK \
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(CPU_INTERRUPT_HARD \
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| CPU_INTERRUPT_TGT_EXT_0 \
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| CPU_INTERRUPT_TGT_EXT_1 \
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| CPU_INTERRUPT_TGT_EXT_2 \
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| CPU_INTERRUPT_TGT_EXT_3 \
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| CPU_INTERRUPT_TGT_EXT_4)
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#endif /* CPU_INTERRUPT_H */
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@ -46,19 +46,6 @@
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#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS
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#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS
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#pragma GCC poison CPU_INTERRUPT_HARD
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#pragma GCC poison CPU_INTERRUPT_EXITTB
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#pragma GCC poison CPU_INTERRUPT_HALT
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#pragma GCC poison CPU_INTERRUPT_DEBUG
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#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
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#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
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#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2
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#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3
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#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4
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#pragma GCC poison CPU_INTERRUPT_TGT_INT_0
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#pragma GCC poison CPU_INTERRUPT_TGT_INT_1
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#pragma GCC poison CPU_INTERRUPT_TGT_INT_2
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#pragma GCC poison CONFIG_ALPHA_DIS
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#pragma GCC poison CONFIG_ALPHA_DIS
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#pragma GCC poison CONFIG_HPPA_DIS
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#pragma GCC poison CONFIG_HPPA_DIS
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#pragma GCC poison CONFIG_I386_DIS
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#pragma GCC poison CONFIG_I386_DIS
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