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https://github.com/Motorhead1991/qemu.git
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Merge remote-tracking branch 'pm-arm/for-upstream' into pm
This commit is contained in:
commit
b9c6cbff76
3 changed files with 121 additions and 42 deletions
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@ -35,6 +35,12 @@ static uint32_t arm1136_cp15_c0_c1[8] =
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static uint32_t arm1136_cp15_c0_c2[8] =
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{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
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static uint32_t arm1176_cp15_c0_c1[8] =
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{ 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
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static uint32_t arm1176_cp15_c0_c2[8] =
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{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
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static uint32_t cpu_arm_find_by_name(const char *name);
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static inline void set_feature(CPUARMState *env, int feature)
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@ -70,13 +76,24 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00090078;
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break;
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case ARM_CPUID_ARM1136_R2:
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case ARM_CPUID_ARM1136:
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/* This is the 1136 r1, which is a v6K core */
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set_feature(env, ARM_FEATURE_V6K);
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/* Fall through */
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case ARM_CPUID_ARM1136_R2:
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/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
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* older core than plain "arm1136". In particular this does not
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* have the v6K features.
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*/
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set_feature(env, ARM_FEATURE_V4T);
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set_feature(env, ARM_FEATURE_V5);
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set_feature(env, ARM_FEATURE_V6);
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set_feature(env, ARM_FEATURE_VFP);
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set_feature(env, ARM_FEATURE_AUXCR);
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/* These ID register values are correct for 1136 but may be wrong
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* for 1136_r2 (in particular r0p2 does not actually implement most
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* of the ID registers).
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*/
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
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@ -85,6 +102,22 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00050078;
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break;
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case ARM_CPUID_ARM1176:
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set_feature(env, ARM_FEATURE_V4T);
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set_feature(env, ARM_FEATURE_V5);
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set_feature(env, ARM_FEATURE_V6);
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set_feature(env, ARM_FEATURE_V6K);
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set_feature(env, ARM_FEATURE_VFP);
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set_feature(env, ARM_FEATURE_AUXCR);
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set_feature(env, ARM_FEATURE_VAPA);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
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memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00050078;
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break;
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case ARM_CPUID_ARM11MPCORE:
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set_feature(env, ARM_FEATURE_V4T);
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set_feature(env, ARM_FEATURE_V5);
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@ -92,6 +125,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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set_feature(env, ARM_FEATURE_V6K);
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set_feature(env, ARM_FEATURE_VFP);
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set_feature(env, ARM_FEATURE_AUXCR);
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set_feature(env, ARM_FEATURE_VAPA);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
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@ -222,6 +256,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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cpu_abort(env, "Bad CPU ID: %x\n", id);
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break;
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}
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V7)) {
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set_feature(env, ARM_FEATURE_VAPA);
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}
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}
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void cpu_reset(CPUARMState *env)
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@ -380,6 +419,7 @@ static const struct arm_cpu_t arm_cpu_names[] = {
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{ ARM_CPUID_ARM1026, "arm1026"},
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{ ARM_CPUID_ARM1136, "arm1136"},
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{ ARM_CPUID_ARM1136_R2, "arm1136-r2"},
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{ ARM_CPUID_ARM1176, "arm1176"},
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{ ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
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{ ARM_CPUID_CORTEXM3, "cortex-m3"},
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{ ARM_CPUID_CORTEXA8, "cortex-a8"},
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@ -948,7 +988,7 @@ static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
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case 6:
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return prot_ro;
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case 7:
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if (!arm_feature (env, ARM_FEATURE_V7))
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if (!arm_feature (env, ARM_FEATURE_V6K))
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return 0;
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return prot_ro;
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default:
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@ -1502,7 +1542,7 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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goto bad_reg;
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}
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/* No cache, so nothing to do except VA->PA translations. */
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if (arm_feature(env, ARM_FEATURE_V6K)) {
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if (arm_feature(env, ARM_FEATURE_VAPA)) {
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switch (crm) {
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case 4:
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if (arm_feature(env, ARM_FEATURE_V7)) {
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@ -1848,6 +1888,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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return 1;
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case ARM_CPUID_ARM1136:
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case ARM_CPUID_ARM1136_R2:
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case ARM_CPUID_ARM1176:
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return 7;
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case ARM_CPUID_ARM11MPCORE:
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return 1;
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