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target/openrisc: Fix cpu_mmu_index

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The code in cpu_mmu_index does not properly honor SR_DME.
This bug has workarounds elsewhere in that we flush the
tlb more often than necessary, on the state changes that
should be reflected in a change of mmu_index.

Fixing this means that we can respect the mmu_index that
is given to tlb_flush.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Richard Henderson 2018-05-22 19:51:00 -07:00 • committed by Stafford Horne
parent fffde6695f
commit b9bed1b9ab
6 changed files with 49 additions and 32 deletions
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15
target/openrisc/interrupt_helper.c
View file

@ -25,16 +25,7 @@
void HELPER(rfe)(CPUOpenRISCState *env)
{
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
#ifndef CONFIG_USER_ONLY
int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^
(cpu->env.esr & (SR_SM | SR_IME | SR_DME));
if (need_flush_tlb) {
CPUState *cs = CPU(cpu);
tlb_flush(cs);
}
#endif
cpu->env.pc = cpu->env.epcr;
cpu->env.lock_addr = -1;
cpu_set_sr(&cpu->env, cpu->env.esr);
env->pc = env->epcr;
env->lock_addr = -1;
cpu_set_sr(env, env->esr);
}