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hw/cxl/events: Add injection of DRAM events
Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event provides information related to DRAM devices. Example injection command in QMP: { "execute": "cxl-inject-dram-event", "arguments": { "path": "/machine/peripheral/cxl-mem0", "log": "informational", "flags": 1, "dpa": 1000, "descriptor": 3, "type": 3, "transaction-type": 192, "channel": 3, "rank": 17, "nibble-mask": 37421234, "bank-group": 7, "bank": 11, "row": 2, "column": 77, "correction-mask": [33, 44, 55,66] }} Acked-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230530133603.16934-7-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -123,4 +123,27 @@ typedef struct CXLEventGenMedia {
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uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE];
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} QEMU_PACKED CXLEventGenMedia;
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/*
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* DRAM Event Record
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* CXL Rev 3.0 Section 8.2.9.2.1.2: Table 8-44
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* All fields little endian.
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*/
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typedef struct CXLEventDram {
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CXLEventRecordHdr hdr;
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uint64_t phys_addr;
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uint8_t descriptor;
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uint8_t type;
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uint8_t transaction_type;
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uint16_t validity_flags;
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uint8_t channel;
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uint8_t rank;
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uint8_t nibble_mask[3];
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uint8_t bank_group;
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uint8_t bank;
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uint8_t row[3];
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uint16_t column;
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uint64_t correction_mask[4];
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uint8_t reserved[0x17];
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} QEMU_PACKED CXLEventDram;
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#endif /* CXL_EVENTS_H */
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