mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 15:53:54 -06:00
Merge branch 'pci' into for_anthony
This commit is contained in:
Michael S. Tsirkin
commit
b907b69dd7
26 changed files with 2606 additions and 276 deletions
322
hw/pci.c
322
hw/pci.c
|
|
@ -23,6 +23,10 @@
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|||
*/
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#include "hw.h"
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#include "pci.h"
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#include "pci_bridge.h"
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#include "pci_internals.h"
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#include "msix.h"
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#include "msi.h"
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#include "monitor.h"
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#include "net.h"
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#include "sysemu.h"
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@ -37,31 +41,10 @@
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# define PCI_DPRINTF(format, ...) do { } while (0)
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#endif
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struct PCIBus {
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BusState qbus;
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int devfn_min;
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pci_set_irq_fn set_irq;
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pci_map_irq_fn map_irq;
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pci_hotplug_fn hotplug;
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DeviceState *hotplug_qdev;
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void *irq_opaque;
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PCIDevice *devices[256];
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PCIDevice *parent_dev;
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target_phys_addr_t mem_base;
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QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
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QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int *irq_count;
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};
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
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static char *pcibus_get_dev_path(DeviceState *dev);
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static struct BusInfo pci_bus_info = {
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struct BusInfo pci_bus_info = {
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.name = "PCI",
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.size = sizeof(PCIBus),
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.print_dev = pcibus_dev_print,
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@ -157,9 +140,9 @@ static void pci_device_reset(PCIDevice *dev)
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dev->irq_state = 0;
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pci_update_irq_status(dev);
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/* Clear all writeable bits */
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pci_set_word(dev->config + PCI_COMMAND,
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pci_get_word(dev->config + PCI_COMMAND) &
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~pci_get_word(dev->wmask + PCI_COMMAND));
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pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
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pci_get_word(dev->wmask + PCI_COMMAND) |
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pci_get_word(dev->w1cmask + PCI_COMMAND));
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dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
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dev->config[PCI_INTERRUPT_LINE] = 0x0;
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for (r = 0; r < PCI_NUM_REGIONS; ++r) {
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@ -293,26 +276,6 @@ PCIBus *pci_register_bus(DeviceState *parent, const char *name,
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return bus;
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}
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static void pci_register_secondary_bus(PCIBus *parent,
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PCIBus *bus,
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PCIDevice *dev,
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pci_map_irq_fn map_irq,
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const char *name)
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{
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qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
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bus->map_irq = map_irq;
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bus->parent_dev = dev;
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QLIST_INIT(&bus->child);
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QLIST_INSERT_HEAD(&parent->child, bus, sibling);
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}
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static void pci_unregister_secondary_bus(PCIBus *bus)
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{
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assert(QLIST_EMPTY(&bus->child));
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QLIST_REMOVE(bus, sibling);
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}
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int pci_bus_num(PCIBus *s)
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{
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if (!s->parent_dev)
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@ -331,7 +294,8 @@ static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
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qemu_get_buffer(f, config, size);
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for (i = 0; i < size; ++i) {
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if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
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if ((config[i] ^ s->config[i]) &
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s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
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qemu_free(config);
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return -EINVAL;
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}
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@ -464,15 +428,18 @@ static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
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}
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/*
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* Parse [[<domain>:]<bus>:]<slot>, return -1 on error
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* Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
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* [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
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*/
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static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
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int pci_parse_devaddr(const char *addr, int *domp, int *busp,
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unsigned int *slotp, unsigned int *funcp)
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{
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const char *p;
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char *e;
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unsigned long val;
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unsigned long dom = 0, bus = 0;
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unsigned slot = 0;
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unsigned int slot = 0;
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unsigned int func = 0;
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p = addr;
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val = strtoul(p, &e, 16);
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@ -494,11 +461,24 @@ static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *s
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}
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}
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if (dom > 0xffff || bus > 0xff || val > 0x1f)
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return -1;
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slot = val;
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if (funcp != NULL) {
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if (*e != '.')
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return -1;
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p = e + 1;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1;
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func = val;
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}
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/* if funcp == NULL func is 0 */
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if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
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return -1;
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if (*e)
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return -1;
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@ -509,6 +489,8 @@ static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *s
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*domp = dom;
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*busp = bus;
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*slotp = slot;
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if (funcp != NULL)
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*funcp = func;
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return 0;
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}
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@ -519,7 +501,7 @@ int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
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if (!strncmp(addr, "pci_addr=", 9)) {
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addr += 9;
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}
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if (pci_parse_devaddr(addr, domp, busp, slotp)) {
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if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
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monitor_printf(mon, "Invalid pci address\n");
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return -1;
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}
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@ -536,7 +518,7 @@ PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
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return pci_find_bus(pci_find_root_bus(0), 0);
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}
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if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
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if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
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return NULL;
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}
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@ -649,6 +631,7 @@ static void pci_config_alloc(PCIDevice *pci_dev)
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pci_dev->config = qemu_mallocz(config_size);
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pci_dev->cmask = qemu_mallocz(config_size);
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pci_dev->wmask = qemu_mallocz(config_size);
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pci_dev->w1cmask = qemu_mallocz(config_size);
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pci_dev->used = qemu_mallocz(config_size);
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}
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@ -657,6 +640,7 @@ static void pci_config_free(PCIDevice *pci_dev)
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qemu_free(pci_dev->config);
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qemu_free(pci_dev->cmask);
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qemu_free(pci_dev->wmask);
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qemu_free(pci_dev->w1cmask);
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qemu_free(pci_dev->used);
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}
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@ -780,16 +764,15 @@ static int pci_unregister_device(DeviceState *dev)
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}
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void pci_register_bar(PCIDevice *pci_dev, int region_num,
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pcibus_t size, int type,
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pcibus_t size, uint8_t type,
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PCIMapIORegionFunc *map_func)
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{
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PCIIORegion *r;
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uint32_t addr;
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pcibus_t wmask;
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if ((unsigned int)region_num >= PCI_NUM_REGIONS)
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return;
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uint64_t wmask;
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assert(region_num >= 0);
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assert(region_num < PCI_NUM_REGIONS);
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if (size & (size-1)) {
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fprintf(stderr, "ERROR: PCI region size must be pow2 "
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"type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
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@ -820,75 +803,6 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
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}
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}
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static uint32_t pci_config_get_io_base(PCIDevice *d,
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uint32_t base, uint32_t base_upper16)
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{
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uint32_t val;
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val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
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if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
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val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
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}
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return val;
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}
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static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
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{
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return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
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<< 16;
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}
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static pcibus_t pci_config_get_pref_base(PCIDevice *d,
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uint32_t base, uint32_t upper)
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{
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pcibus_t tmp;
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pcibus_t val;
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tmp = (pcibus_t)pci_get_word(d->config + base);
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val = (tmp & PCI_PREF_RANGE_MASK) << 16;
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if (tmp & PCI_PREF_RANGE_TYPE_64) {
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val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
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}
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return val;
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}
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static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
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{
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pcibus_t base;
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if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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base = pci_config_get_io_base(bridge,
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PCI_IO_BASE, PCI_IO_BASE_UPPER16);
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} else {
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if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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base = pci_config_get_pref_base(
|
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bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
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} else {
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base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
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}
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}
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return base;
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}
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|
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static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
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{
|
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pcibus_t limit;
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if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
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limit = pci_config_get_io_base(bridge,
|
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PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
|
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limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */
|
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} else {
|
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if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
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limit = pci_config_get_pref_base(
|
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bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
|
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} else {
|
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limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
|
||||
}
|
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limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
|
||||
}
|
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return limit;
|
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}
|
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|
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static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
|
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uint8_t type)
|
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{
|
||||
|
|
@ -1089,7 +1003,10 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
|
|||
|
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for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
|
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uint8_t wmask = d->wmask[addr + i];
|
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uint8_t w1cmask = d->w1cmask[addr + i];
|
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assert(!(wmask & w1cmask));
|
||||
d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
|
||||
d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
|
||||
}
|
||||
if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
|
||||
ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
|
||||
|
|
@ -1121,6 +1038,23 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
|
|||
pci_change_irq_level(pci_dev, irq_num, change);
|
||||
}
|
||||
|
||||
bool pci_msi_enabled(PCIDevice *dev)
|
||||
{
|
||||
return msix_enabled(dev) || msi_enabled(dev);
|
||||
}
|
||||
|
||||
void pci_msi_notify(PCIDevice *dev, unsigned int vector)
|
||||
{
|
||||
if (msix_enabled(dev)) {
|
||||
msix_notify(dev, vector);
|
||||
} else if (msi_enabled(dev)) {
|
||||
msi_notify(dev, vector);
|
||||
} else {
|
||||
/* MSI/MSI-X must be enabled */
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/***********************************************************/
|
||||
/* monitor info on PCI */
|
||||
|
||||
|
|
@ -1534,20 +1468,12 @@ PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
|
|||
return res;
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
PCIDevice dev;
|
||||
PCIBus bus;
|
||||
uint32_t vid;
|
||||
uint32_t did;
|
||||
} PCIBridge;
|
||||
|
||||
|
||||
static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
|
||||
{
|
||||
pci_update_mappings(d);
|
||||
}
|
||||
|
||||
static void pci_bridge_update_mappings(PCIBus *b)
|
||||
void pci_bridge_update_mappings(PCIBus *b)
|
||||
{
|
||||
PCIBus *child;
|
||||
|
||||
|
|
@ -1558,23 +1484,6 @@ static void pci_bridge_update_mappings(PCIBus *b)
|
|||
}
|
||||
}
|
||||
|
||||
static void pci_bridge_write_config(PCIDevice *d,
|
||||
uint32_t address, uint32_t val, int len)
|
||||
{
|
||||
pci_default_write_config(d, address, val, len);
|
||||
|
||||
if (/* io base/limit */
|
||||
ranges_overlap(address, len, PCI_IO_BASE, 2) ||
|
||||
|
||||
/* memory base/limit, prefetchable base/limit and
|
||||
io base/limit upper 16 */
|
||||
ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
|
||||
PCIBridge *s = container_of(d, PCIBridge, dev);
|
||||
PCIBus *secondary_bus = &s->bus;
|
||||
pci_bridge_update_mappings(secondary_bus);
|
||||
}
|
||||
}
|
||||
|
||||
PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
|
||||
{
|
||||
PCIBus *sec;
|
||||
|
|
@ -1618,54 +1527,6 @@ PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
|
|||
return bus->devices[PCI_DEVFN(slot, function)];
|
||||
}
|
||||
|
||||
static int pci_bridge_initfn(PCIDevice *dev)
|
||||
{
|
||||
PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
|
||||
|
||||
pci_config_set_vendor_id(s->dev.config, s->vid);
|
||||
pci_config_set_device_id(s->dev.config, s->did);
|
||||
|
||||
pci_set_word(dev->config + PCI_STATUS,
|
||||
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
|
||||
pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
|
||||
dev->config[PCI_HEADER_TYPE] =
|
||||
(dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
|
||||
PCI_HEADER_TYPE_BRIDGE;
|
||||
pci_set_word(dev->config + PCI_SEC_STATUS,
|
||||
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pci_bridge_exitfn(PCIDevice *pci_dev)
|
||||
{
|
||||
PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
|
||||
PCIBus *bus = &s->bus;
|
||||
pci_unregister_secondary_bus(bus);
|
||||
return 0;
|
||||
}
|
||||
|
||||
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, bool multifunction,
|
||||
uint16_t vid, uint16_t did,
|
||||
pci_map_irq_fn map_irq, const char *name)
|
||||
{
|
||||
PCIDevice *dev;
|
||||
PCIBridge *s;
|
||||
|
||||
dev = pci_create_multifunction(bus, devfn, multifunction, "pci-bridge");
|
||||
qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
|
||||
qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
|
||||
qdev_init_nofail(&dev->qdev);
|
||||
|
||||
s = DO_UPCAST(PCIBridge, dev, dev);
|
||||
pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
|
||||
return &s->bus;
|
||||
}
|
||||
|
||||
PCIDevice *pci_bridge_get_device(PCIBus *bus)
|
||||
{
|
||||
return bus->parent_dev;
|
||||
}
|
||||
|
||||
static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
|
||||
{
|
||||
PCIDevice *pci_dev = (PCIDevice *)qdev;
|
||||
|
|
@ -1696,7 +1557,8 @@ static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
|
|||
pci_dev->romfile = qemu_strdup(info->romfile);
|
||||
pci_add_option_rom(pci_dev);
|
||||
|
||||
if (qdev->hotplugged) {
|
||||
if (bus->hotplug) {
|
||||
/* lower layer must check qdev->hotplugged */
|
||||
rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
|
||||
if (rc != 0) {
|
||||
int r = pci_unregister_device(&pci_dev->qdev);
|
||||
|
|
@ -1864,11 +1726,25 @@ static void pci_del_option_rom(PCIDevice *pdev)
|
|||
pdev->rom_offset = 0;
|
||||
}
|
||||
|
||||
/* Reserve space and add capability to the linked list in pci config space */
|
||||
int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id,
|
||||
uint8_t offset, uint8_t size)
|
||||
/*
|
||||
* if !offset
|
||||
* Reserve space and add capability to the linked list in pci config space
|
||||
*
|
||||
* if offset = 0,
|
||||
* Find and reserve space and add capability to the linked list
|
||||
* in pci config space */
|
||||
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
|
||||
uint8_t offset, uint8_t size)
|
||||
{
|
||||
uint8_t *config = pdev->config + offset;
|
||||
uint8_t *config;
|
||||
if (!offset) {
|
||||
offset = pci_find_space(pdev, size);
|
||||
if (!offset) {
|
||||
return -ENOSPC;
|
||||
}
|
||||
}
|
||||
|
||||
config = pdev->config + offset;
|
||||
config[PCI_CAP_LIST_ID] = cap_id;
|
||||
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
|
||||
pdev->config[PCI_CAPABILITY_LIST] = offset;
|
||||
|
|
@ -1881,17 +1757,6 @@ int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id,
|
|||
return offset;
|
||||
}
|
||||
|
||||
/* Find and reserve space and add capability to the linked list
|
||||
* in pci config space */
|
||||
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
||||
{
|
||||
uint8_t offset = pci_find_space(pdev, size);
|
||||
if (!offset) {
|
||||
return -ENOSPC;
|
||||
}
|
||||
return pci_add_capability_at_offset(pdev, cap_id, offset, size);
|
||||
}
|
||||
|
||||
/* Unlink capability from the pci config space. */
|
||||
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
||||
{
|
||||
|
|
@ -1901,6 +1766,7 @@ void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
|||
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
|
||||
/* Make capability writeable again */
|
||||
memset(pdev->wmask + offset, 0xff, size);
|
||||
memset(pdev->w1cmask + offset, 0, size);
|
||||
/* Clear cmask as device-specific registers can't be checked */
|
||||
memset(pdev->cmask + offset, 0, size);
|
||||
memset(pdev->used + offset, 0, size);
|
||||
|
|
@ -1971,23 +1837,3 @@ static char *pcibus_get_dev_path(DeviceState *dev)
|
|||
return strdup(path);
|
||||
}
|
||||
|
||||
static PCIDeviceInfo bridge_info = {
|
||||
.qdev.name = "pci-bridge",
|
||||
.qdev.size = sizeof(PCIBridge),
|
||||
.init = pci_bridge_initfn,
|
||||
.exit = pci_bridge_exitfn,
|
||||
.config_write = pci_bridge_write_config,
|
||||
.is_bridge = 1,
|
||||
.qdev.props = (Property[]) {
|
||||
DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
|
||||
DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
}
|
||||
};
|
||||
|
||||
static void pci_register_devices(void)
|
||||
{
|
||||
pci_qdev_register(&bridge_info);
|
||||
}
|
||||
|
||||
device_init(pci_register_devices)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue