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-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1 iQEcBAABAgAGBQJY/zFbAAoJEO8Ells5jWIR7LgH/A6lWkODVSKihnibRH82J9oe rTsDdLgAGAMAur++tmNorPadZyMe/2+Cu0VsiIv591ldILruN6+jJydBzFtWFYE5 JQKa2VSTDu6bHPhr/UpRnWLhGzaJogklJR6YLkonDJznb1UnnTwEZ8c8+XD4gWLo byo/dYF1yMnpVxSak/FkmCmwxc2K7s7P+r4FWO2CgAgY28F+/qERWJMbl1iUevQP E1PC/XXEvhMdxi+6oYmWACdbW9/KwC5KKVELsQWYU1DcpQ7rWXCtA/mtKxvX+ePw 7CUK9ldeFXHE8uWVDnh3cWUL65Q8OtZarjMbrnN7xzcQDhMysStvVNS4QckN6/I= =PEvc -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging # gpg: Signature made Tue 25 Apr 2017 12:22:03 BST # gpg: using RSA key 0xEF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * remotes/jasowang/tags/net-pull-request: COLO-compare: Optimize tcp compare trace event COLO-compare: Optimize tcp compare for option field slirp: add a fake NC-SI backend aspeed: add a FTGMAC100 nic net/ftgmac100: add a 'aspeed' property net: add FTGMAC100 support hw/net: add MII definitions colo-compare: Fix old packet check bug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
b8c7193fe9
15 changed files with 1770 additions and 37 deletions
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@ -20,6 +20,7 @@
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/ssi/aspeed_smc.h"
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#include "hw/watchdog/wdt_aspeed.h"
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#include "hw/net/ftgmac100.h"
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#define ASPEED_SPIS_NUM 2
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@ -39,6 +40,7 @@ typedef struct AspeedSoCState {
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AspeedSMCState spi[ASPEED_SPIS_NUM];
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AspeedSDMCState sdmc;
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AspeedWDTState wdt;
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FTGMAC100State ftgmac100;
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} AspeedSoCState;
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#define TYPE_ASPEED_SOC "aspeed-soc"
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64
include/hw/net/ftgmac100.h
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64
include/hw/net/ftgmac100.h
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@ -0,0 +1,64 @@
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/*
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* Faraday FTGMAC100 Gigabit Ethernet
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*
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* Copyright (C) 2016-2017, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef FTGMAC100_H
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#define FTGMAC100_H
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#define TYPE_FTGMAC100 "ftgmac100"
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#define FTGMAC100(obj) OBJECT_CHECK(FTGMAC100State, (obj), TYPE_FTGMAC100)
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#include "hw/sysbus.h"
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#include "net/net.h"
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typedef struct FTGMAC100State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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NICState *nic;
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NICConf conf;
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qemu_irq irq;
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MemoryRegion iomem;
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uint8_t *frame;
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uint32_t irq_state;
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uint32_t isr;
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uint32_t ier;
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uint32_t rx_enabled;
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uint32_t rx_ring;
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uint32_t rx_descriptor;
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uint32_t tx_ring;
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uint32_t tx_descriptor;
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uint32_t math[2];
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uint32_t rbsr;
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uint32_t itc;
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uint32_t aptcr;
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uint32_t dblac;
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uint32_t revr;
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uint32_t fear1;
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uint32_t tpafcr;
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uint32_t maccr;
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uint32_t phycr;
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uint32_t phydata;
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uint32_t fcr;
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uint32_t phy_status;
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uint32_t phy_control;
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uint32_t phy_advertise;
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uint32_t phy_int;
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uint32_t phy_int_mask;
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bool aspeed;
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uint32_t txdes0_edotr;
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uint32_t rxdes0_edorr;
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} FTGMAC100State;
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#endif
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@ -22,13 +22,20 @@
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#define MII_H
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/* PHY registers */
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#define MII_BMCR 0
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#define MII_BMSR 1
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#define MII_PHYID1 2
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#define MII_PHYID2 3
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#define MII_ANAR 4
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#define MII_ANLPAR 5
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#define MII_ANER 6
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#define MII_BMCR 0 /* Basic mode control register */
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#define MII_BMSR 1 /* Basic mode status register */
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#define MII_PHYID1 2 /* ID register 1 */
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#define MII_PHYID2 3 /* ID register 2 */
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#define MII_ANAR 4 /* Autonegotiation advertisement */
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#define MII_ANLPAR 5 /* Autonegotiation lnk partner abilities */
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#define MII_ANER 6 /* Autonegotiation expansion */
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#define MII_ANNP 7 /* Autonegotiation next page */
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#define MII_ANLPRNP 8 /* Autonegotiation link partner rx next page */
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#define MII_CTRL1000 9 /* 1000BASE-T control */
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#define MII_STAT1000 10 /* 1000BASE-T status */
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#define MII_MDDACR 13 /* MMD access control */
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#define MII_MDDAADR 14 /* MMD access address data */
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#define MII_EXTSTAT 15 /* Extended Status */
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#define MII_NSR 16
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#define MII_LBREMR 17
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#define MII_REC 18
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@ -38,19 +45,33 @@
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/* PHY registers fields */
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#define MII_BMCR_RESET (1 << 15)
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#define MII_BMCR_LOOPBACK (1 << 14)
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#define MII_BMCR_SPEED (1 << 13)
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#define MII_BMCR_AUTOEN (1 << 12)
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#define MII_BMCR_FD (1 << 8)
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#define MII_BMCR_SPEED100 (1 << 13) /* LSB of Speed (100) */
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#define MII_BMCR_SPEED MII_BMCR_SPEED100
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#define MII_BMCR_AUTOEN (1 << 12) /* Autonegotiation enable */
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#define MII_BMCR_PDOWN (1 << 11) /* Enable low power state */
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#define MII_BMCR_ISOLATE (1 << 10) /* Isolate data paths from MII */
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#define MII_BMCR_ANRESTART (1 << 9) /* Auto negotiation restart */
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#define MII_BMCR_FD (1 << 8) /* Set duplex mode */
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#define MII_BMCR_CTST (1 << 7) /* Collision test */
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#define MII_BMCR_SPEED1000 (1 << 6) /* MSB of Speed (1000) */
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#define MII_BMSR_100TX_FD (1 << 14)
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#define MII_BMSR_100TX_HD (1 << 13)
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#define MII_BMSR_10T_FD (1 << 12)
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#define MII_BMSR_10T_HD (1 << 11)
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#define MII_BMSR_MFPS (1 << 6)
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#define MII_BMSR_AN_COMP (1 << 5)
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#define MII_BMSR_AUTONEG (1 << 3)
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#define MII_BMSR_LINK_ST (1 << 2)
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#define MII_BMSR_100TX_FD (1 << 14) /* Can do 100mbps, full-duplex */
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#define MII_BMSR_100TX_HD (1 << 13) /* Can do 100mbps, half-duplex */
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#define MII_BMSR_10T_FD (1 << 12) /* Can do 10mbps, full-duplex */
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#define MII_BMSR_10T_HD (1 << 11) /* Can do 10mbps, half-duplex */
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#define MII_BMSR_100T2_FD (1 << 10) /* Can do 100mbps T2, full-duplex */
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#define MII_BMSR_100T2_HD (1 << 9) /* Can do 100mbps T2, half-duplex */
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#define MII_BMSR_EXTSTAT (1 << 8) /* Extended status in register 15 */
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#define MII_BMSR_MFPS (1 << 6) /* MII Frame Preamble Suppression */
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#define MII_BMSR_AN_COMP (1 << 5) /* Auto-negotiation complete */
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#define MII_BMSR_RFAULT (1 << 4) /* Remote fault */
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#define MII_BMSR_AUTONEG (1 << 3) /* Able to do auto-negotiation */
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#define MII_BMSR_LINK_ST (1 << 2) /* Link status */
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#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
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#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
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#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymetric pause */
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#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
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#define MII_ANAR_TXFD (1 << 8)
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#define MII_ANAR_TX (1 << 7)
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#define MII_ANAR_10FD (1 << 6)
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@ -58,17 +79,31 @@
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#define MII_ANAR_CSMACD (1 << 0)
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#define MII_ANLPAR_ACK (1 << 14)
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#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
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#define MII_ANLPAR_PAUSE (1 << 10) /* can pause */
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#define MII_ANLPAR_TXFD (1 << 8)
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#define MII_ANLPAR_TX (1 << 7)
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#define MII_ANLPAR_10FD (1 << 6)
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#define MII_ANLPAR_10 (1 << 5)
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#define MII_ANLPAR_CSMACD (1 << 0)
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#define MII_ANER_NWAY (1 << 0) /* Can do N-way auto-nego */
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#define MII_CTRL1000_FULL (1 << 9) /* 1000BASE-T full duplex */
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#define MII_CTRL1000_HALF (1 << 8) /* 1000BASE-T half duplex */
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#define MII_STAT1000_FULL (1 << 11) /* 1000BASE-T full duplex */
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#define MII_STAT1000_HALF (1 << 10) /* 1000BASE-T half duplex */
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/* List of vendor identifiers */
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/* RealTek 8201 */
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#define RTL8201CP_PHYID1 0x0000
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#define RTL8201CP_PHYID2 0x8201
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/* RealTek 8211E */
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#define RTL8211E_PHYID1 0x001c
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#define RTL8211E_PHYID2 0xc915
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/* National Semiconductor DP83848 */
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#define DP83848_PHYID1 0x2000
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#define DP83848_PHYID2 0x5c90
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