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RISC-V: Adding T-Head multiply-accumulate instructions

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This patch adds support for the T-Head MAC instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-8-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner 2023-01-31 21:20:06 +01:00 • committed by Alistair Francis
parent 3290933853
commit b8a5832b87
5 changed files with 96 additions and 1 deletions
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1
target/riscv/cpu.h
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@ -478,6 +478,7 @@ struct RISCVCPUConfig {
bool ext_xtheadbs;
bool ext_xtheadcmo;
bool ext_xtheadcondmov;
bool ext_xtheadmac;
bool ext_xtheadsync;
bool ext_XVentanaCondOps;