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docs: updates on the POWER9 XIVE interrupt controller documentation

Browse source 
This includes various small updates and a better description of the
chosen interrupt mode resulting from the combination of the 'ic-mode'
machine option, the 'kernel_irqchip' option, guest support and KVM
support.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190612160425.27670-1-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2019-06-12 18:04:25 +02:00 • committed by David Gibson
parent fad189d1f6
commit b87a0100cd
2 changed files with 111 additions and 10 deletions
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9
docs/specs/ppc-xive.rst
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@ -20,10 +20,11 @@ The XIVE IC is composed of three sub-engines, each taking care of a
processing layer of external interrupts:
- Interrupt Virtualization Source Engine (IVSE), or Source Controller
(SC). These are found in PCI PHBs, in the PSI host bridge
controller, but also inside the main controller for the core IPIs
and other sub-chips (NX, CAP, NPU) of the chip/processor. They are
configured to feed the IVRE with events.
(SC). These are found in PCI PHBs, in the Processor Service
Interface (PSI) host bridge Controller, but also inside the main
controller for the core IPIs and other sub-chips (NX, CAP, NPU) of
the chip/processor. They are configured to feed the IVRE with
events.
- Interrupt Virtualization Routing Engine (IVRE) or Virtualization
Controller (VC). It handles event coalescing and perform interrupt
routing by matching an event source number with an Event