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target-xtensa: implement FP0 conversions
These are FP to integer and integer to FP conversion opcodes. See ISA, 4.3.10 for more details. Note that ISA description for utrunc.s is currently incorrect and will be fixed in future revisions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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3 changed files with 89 additions and 0 deletions
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@ -1933,6 +1933,54 @@ static void disas_xtensa_insn(DisasContext *dc)
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cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
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break;
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case 8: /*ROUND.Sf*/
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case 9: /*TRUNC.Sf*/
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case 10: /*FLOOR.Sf*/
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case 11: /*CEIL.Sf*/
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case 14: /*UTRUNC.Sf*/
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gen_window_check1(dc, RRR_R);
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{
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static const unsigned rounding_mode_const[] = {
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float_round_nearest_even,
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float_round_to_zero,
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float_round_down,
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float_round_up,
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[6] = float_round_to_zero,
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};
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TCGv_i32 rounding_mode = tcg_const_i32(
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rounding_mode_const[OP2 & 7]);
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TCGv_i32 scale = tcg_const_i32(RRR_T);
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if (OP2 == 14) {
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gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
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rounding_mode, scale);
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} else {
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gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
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rounding_mode, scale);
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}
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tcg_temp_free(rounding_mode);
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tcg_temp_free(scale);
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}
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break;
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case 12: /*FLOAT.Sf*/
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case 13: /*UFLOAT.Sf*/
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gen_window_check1(dc, RRR_S);
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{
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TCGv_i32 scale = tcg_const_i32(-RRR_T);
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if (OP2 == 13) {
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gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
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cpu_R[RRR_S], scale);
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} else {
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gen_helper_itof(cpu_FR[RRR_R], cpu_env,
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cpu_R[RRR_S], scale);
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}
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tcg_temp_free(scale);
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}
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break;
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case 15: /*FP1OP*/
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switch (RRR_T) {
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case 0: /*MOV.Sf*/
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