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i386: Add support to get/set/migrate Intel Processor Trace feature

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Add Intel Processor Trace related definition. It also add
corresponding part to kvm_get/set_msr and vmstate.

Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Message-Id: <1520182116-16485-2-git-send-email-luwei.kang@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Chao Peng 2018-03-05 00:48:36 +08:00 • committed by Eduardo Habkost
parent e37a5c7fa4
commit b77146e9a1
3 changed files with 111 additions and 0 deletions
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51
target/i386/kvm.c
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@ -1815,6 +1815,25 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
}
}
if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
0x14, 1, R_EAX) & 0x7;
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
env->msr_rtit_ctrl);
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
env->msr_rtit_status);
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
env->msr_rtit_output_base);
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
env->msr_rtit_output_mask);
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
env->msr_rtit_cr3_match);
for (i = 0; i < addr_num; i++) {
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
env->msr_rtit_addrs[i]);
}
}
/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
* kvm_put_msr_feature_control. */
@ -2128,6 +2147,20 @@ static int kvm_get_msrs(X86CPU *cpu)
}
}
if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
int addr_num =
kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
for (i = 0; i < addr_num; i++) {
kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
}
}
ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
if (ret < 0) {
return ret;
@ -2368,6 +2401,24 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_SPEC_CTRL:
env->spec_ctrl = msrs[i].data;
break;
case MSR_IA32_RTIT_CTL:
env->msr_rtit_ctrl = msrs[i].data;
break;
case MSR_IA32_RTIT_STATUS:
env->msr_rtit_status = msrs[i].data;
break;
case MSR_IA32_RTIT_OUTPUT_BASE:
env->msr_rtit_output_base = msrs[i].data;
break;
case MSR_IA32_RTIT_OUTPUT_MASK:
env->msr_rtit_output_mask = msrs[i].data;
break;
case MSR_IA32_RTIT_CR3_MATCH:
env->msr_rtit_cr3_match = msrs[i].data;
break;
case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
break;
}
}