motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-07-29 05:13:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target-or32: Add interrupt support

Browse source 
Add OpenRISC interrupt support.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Jia Liu 2012-07-20 15:50:41 +08:00 • committed by Blue Swirl
parent 726fe04572
commit b6a71ef7e0
6 changed files with 151 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

57
target-openrisc/interrupt_helper.c Normal file
View file

@ -0,0 +1,57 @@
/*
* OpenRISC interrupt helper routines
*
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
* Feng Gao <gf91597@gmail.com>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "cpu.h"
#include "helper.h"
void HELPER(rfe)(CPUOpenRISCState *env)
{
OpenRISCCPU *cpu = OPENRISC_CPU(ENV_GET_CPU(env));
#ifndef CONFIG_USER_ONLY
int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^
(cpu->env.esr & (SR_SM | SR_IME | SR_DME));
#endif
cpu->env.pc = cpu->env.epcr;
cpu->env.npc = cpu->env.epcr;
cpu->env.sr = cpu->env.esr;
#ifndef CONFIG_USER_ONLY
if (cpu->env.sr & SR_DME) {
cpu->env.tlb->cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_data;
} else {
cpu->env.tlb->cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_nommu;
}
if (cpu->env.sr & SR_IME) {
cpu->env.tlb->cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_code;
} else {
cpu->env.tlb->cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_nommu;
}
if (need_flush_tlb) {
tlb_flush(&cpu->env, 1);
}
#endif
cpu->env.interrupt_request |= CPU_INTERRUPT_EXITTB;
}