motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-01 14:53:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target-or32: Add interrupt support

Browse source 
Add OpenRISC interrupt support.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Jia Liu 2012-07-20 15:50:41 +08:00 • committed by Blue Swirl
parent 726fe04572
commit b6a71ef7e0
6 changed files with 151 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

44
target-openrisc/interrupt.c
View file

@ -27,4 +27,48 @@
void do_interrupt(CPUOpenRISCState *env)
{
#ifndef CONFIG_USER_ONLY
if (env->flags & D_FLAG) { /* Delay Slot insn */
env->flags &= ~D_FLAG;
env->sr |= SR_DSX;
if (env->exception_index == EXCP_TICK ||
env->exception_index == EXCP_INT ||
env->exception_index == EXCP_SYSCALL ||
env->exception_index == EXCP_FPE) {
env->epcr = env->jmp_pc;
} else {
env->epcr = env->pc - 4;
}
} else {
if (env->exception_index == EXCP_TICK ||
env->exception_index == EXCP_INT ||
env->exception_index == EXCP_SYSCALL ||
env->exception_index == EXCP_FPE) {
env->epcr = env->npc;
} else {
env->epcr = env->pc;
}
}
/* For machine-state changed between user-mode and supervisor mode,
we need flush TLB when we enter&exit EXCP. */
tlb_flush(env, 1);
env->esr = env->sr;
env->sr &= ~SR_DME;
env->sr &= ~SR_IME;
env->sr |= SR_SM;
env->sr &= ~SR_IEE;
env->sr &= ~SR_TEE;
env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
if (env->exception_index > 0 && env->exception_index < EXCP_NR) {
env->pc = (env->exception_index << 8);
} else {
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
}
#endif
env->exception_index = -1;
}