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target/xtensa: sim: instantiate local memories

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Xtensa core may have a number of RAM and ROM areas configured. Record
their size and location from the core configuration overlay and
instantiate them as RAM regions in the SIM machine.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2017-02-22 18:59:32 -08:00
parent 10f25e4844
commit b68755c142
3 changed files with 207 additions and 9 deletions
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16
target/xtensa/cpu.h
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@ -212,6 +212,7 @@ enum {
#define MAX_NCCOMPARE 3
#define MAX_TLB_WAY_SIZE 8
#define MAX_NDBREAK 2
#define MAX_NMEMORY 4
#define REGION_PAGE_MASK 0xe0000000
@ -321,6 +322,14 @@ typedef struct XtensaCcompareTimer {
QEMUTimer *timer;
} XtensaCcompareTimer;
typedef struct XtensaMemory {
unsigned num;
struct XtensaMemoryRegion {
uint32_t addr;
uint32_t size;
} location[MAX_NMEMORY];
} XtensaMemory;
struct XtensaConfig {
const char *name;
uint64_t options;
@ -352,6 +361,13 @@ struct XtensaConfig {
unsigned dcache_ways;
uint32_t memctl_mask;
XtensaMemory instrom;
XtensaMemory instram;
XtensaMemory datarom;
XtensaMemory dataram;
XtensaMemory sysrom;
XtensaMemory sysram;
uint32_t configid[2];
uint32_t clock_freq_khz;