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target/riscv: Remove obsolete sfence.vm instruction

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Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jason Chien <jason.chien@sifive.com>
Message-ID: <20250205-b4-ctr_upstream_v6-v6-1-439d8e06c8ef@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Rajnesh Kanwal 2025-02-05 11:18:45 +00:00 • committed by Alistair Francis
parent 4a16a1a7ad
commit b638f679fe
2 changed files with 0 additions and 6 deletions
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1
target/riscv/insn32.decode
View file

@ -119,7 +119,6 @@ sret 0001000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
# *** NMI *** # *** NMI ***
mnret 0111000 00010 00000 000 00000 1110011 mnret 0111000 00010 00000 000 00000 1110011

5
target/riscv/insn_trans/trans_privileged.c.inc
View file

@ -147,8 +147,3 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
#endif #endif
return false; return false;
} }
static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
{
return false;
}