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target/riscv: csr: Hook debug CSR read/write

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This adds debug CSR read/write support to the RISC-V CSR RW table.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-4-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2022-04-21 08:33:21 +08:00 • committed by Alistair Francis
parent 1acdb3b013
commit b6092544fc
4 changed files with 90 additions and 0 deletions
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2
target/riscv/debug.h
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@ -109,4 +109,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
void riscv_trigger_init(CPURISCVState *env);
#endif /* RISCV_DEBUG_H */