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target/riscv: debug: Implement debug related TCGCPUOps
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint} TCGCPUOps and hook them into riscv_tcg_ops. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220421003324.1134983-2-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -337,3 +337,78 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
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return write_func(env, env->trigger_cur, tdata_index, val);
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}
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void riscv_cpu_debug_excp_handler(CPUState *cs)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (cs->watchpoint_hit) {
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if (cs->watchpoint_hit->flags & BP_CPU) {
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cs->watchpoint_hit = NULL;
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riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
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}
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} else {
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if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
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riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
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}
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}
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}
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bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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CPUBreakpoint *bp;
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target_ulong ctrl;
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target_ulong pc;
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int i;
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QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
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for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
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ctrl = env->type2_trig[i].mcontrol;
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pc = env->type2_trig[i].maddress;
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if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
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/* check U/S/M bit against current privilege level */
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if ((ctrl >> 3) & BIT(env->priv)) {
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return true;
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}
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}
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}
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}
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return false;
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}
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bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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target_ulong ctrl;
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target_ulong addr;
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int flags;
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int i;
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for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
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ctrl = env->type2_trig[i].mcontrol;
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addr = env->type2_trig[i].maddress;
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flags = 0;
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if (ctrl & TYPE2_LOAD) {
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flags |= BP_MEM_READ;
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}
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if (ctrl & TYPE2_STORE) {
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flags |= BP_MEM_WRITE;
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}
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if ((wp->flags & flags) && (wp->vaddr == addr)) {
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/* check U/S/M bit against current privilege level */
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if ((ctrl >> 3) & BIT(env->priv)) {
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return true;
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}
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}
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}
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return false;
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}
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