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tcg: Merge INDEX_op_mov_{i32,i64}
Begin to rely on TCGOp.type to discriminate operations, rather than two different opcodes. Convert mov first. Introduce TCG_OPF_INT in order to keep opcode dumps the same. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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parent
48e8de684a
commit
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17 changed files with 32 additions and 58 deletions
32
tcg/tcg.c
32
tcg/tcg.c
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@ -2187,7 +2187,9 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
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case INDEX_op_qemu_st_i128:
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return TCG_TARGET_HAS_qemu_ldst_i128;
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case INDEX_op_mov_i32:
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case INDEX_op_mov:
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return has_type;
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case INDEX_op_setcond_i32:
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case INDEX_op_brcond_i32:
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case INDEX_op_movcond_i32:
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@ -2269,7 +2271,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
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case INDEX_op_setcond2_i32:
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return TCG_TARGET_REG_BITS == 32;
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case INDEX_op_mov_i64:
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case INDEX_op_setcond_i64:
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case INDEX_op_brcond_i64:
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case INDEX_op_movcond_i64:
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@ -2840,18 +2841,23 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
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col += ne_fprintf(f, ",%s", t);
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}
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} else {
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col += ne_fprintf(f, " %s ", def->name);
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if (def->flags & TCG_OPF_INT) {
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col += ne_fprintf(f, " %s_i%d ",
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def->name,
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8 * tcg_type_size(TCGOP_TYPE(op)));
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} else if (def->flags & TCG_OPF_VECTOR) {
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col += ne_fprintf(f, "%s v%d,e%d,",
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def->name,
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8 * tcg_type_size(TCGOP_TYPE(op)),
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8 << TCGOP_VECE(op));
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} else {
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col += ne_fprintf(f, " %s ", def->name);
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}
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nb_oargs = def->nb_oargs;
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nb_iargs = def->nb_iargs;
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nb_cargs = def->nb_cargs;
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if (def->flags & TCG_OPF_VECTOR) {
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col += ne_fprintf(f, "v%d,e%d,",
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8 * tcg_type_size(TCGOP_TYPE(op)),
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8 << TCGOP_VECE(op));
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}
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k = 0;
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for (i = 0; i < nb_oargs; i++) {
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const char *sep = k ? "," : "";
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@ -4144,8 +4150,7 @@ liveness_pass_1(TCGContext *s)
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/* Incorporate constraints for this operand. */
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switch (opc) {
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case INDEX_op_mov_i32:
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case INDEX_op_mov_i64:
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case INDEX_op_mov:
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/* Note that these are TCG_OPF_NOT_PRESENT and do not
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have proper constraints. That said, special case
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moves to propagate preferences backward. */
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@ -4304,7 +4309,7 @@ liveness_pass_2(TCGContext *s)
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}
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/* Outputs become available. */
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if (opc == INDEX_op_mov_i32 || opc == INDEX_op_mov_i64) {
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if (opc == INDEX_op_mov) {
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arg_ts = arg_temp(op->args[0]);
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dir_ts = arg_ts->state_ptr;
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if (dir_ts) {
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@ -6435,8 +6440,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
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TCGOpcode opc = op->opc;
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switch (opc) {
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case INDEX_op_mov_i32:
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case INDEX_op_mov_i64:
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case INDEX_op_mov:
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case INDEX_op_mov_vec:
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tcg_reg_alloc_mov(s, op);
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break;
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