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target/riscv: Add cycle & instret privilege mode filtering support

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QEMU only calculates dummy cycles and instructions, so there is no
actual means to stop the icount in QEMU. Hence this patch merely adds
the functionality of accessing the cfg registers, and cause no actual
effects on the counting of cycle and instret counters.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-5-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Kaiwen Xue 2024-07-11 15:31:08 -07:00 • committed by Alistair Francis
parent 6d1e3893cf
commit b54a84c15e
2 changed files with 149 additions and 1 deletions
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12
target/riscv/cpu_bits.h
View file

@ -926,6 +926,18 @@ typedef enum RISCVException {
#define MHPMEVENT_BIT_VUINH BIT_ULL(58)
#define MHPMEVENTH_BIT_VUINH BIT(26)
#define MHPMEVENT_FILTER_MASK (MHPMEVENT_BIT_MINH | \
MHPMEVENT_BIT_SINH | \
MHPMEVENT_BIT_UINH | \
MHPMEVENT_BIT_VSINH | \
MHPMEVENT_BIT_VUINH)
#define MHPMEVENTH_FILTER_MASK (MHPMEVENTH_BIT_MINH | \
MHPMEVENTH_BIT_SINH | \
MHPMEVENTH_BIT_UINH | \
MHPMEVENTH_BIT_VSINH | \
MHPMEVENTH_BIT_VUINH)
#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000)
#define MHPMEVENT_IDX_MASK 0xFFFFF
#define MHPMEVENT_SSCOF_RESVD 16