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translator: merge max_insns into DisasContextBase

Browse source 
While at it, use int for both num_insns and max_insns to make
sure we have same-type comparisons.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Emilio G. Cota 2018-02-19 20:51:58 -05:00 • committed by Richard Henderson
parent 6cd79443d3
commit b542683d77
8 changed files with 27 additions and 42 deletions
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6
target/alpha/translate.c
View file

@ -2919,8 +2919,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
return ret;
}
static int alpha_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cpu, int max_insns)
static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUAlphaState *env = cpu->env_ptr;
@ -2959,8 +2958,7 @@ static int alpha_tr_init_disas_context(DisasContextBase *dcbase,
mask = TARGET_PAGE_MASK;
}
bound = -(ctx->base.pc_first | mask) / 4;
return MIN(max_insns, bound);
ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
}
static void alpha_tr_tb_start(DisasContextBase *db, CPUState *cpu)

8
target/arm/translate-a64.c
View file

@ -13224,8 +13224,8 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
free_tmp_a64(s);
}
static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cpu, int max_insns)
static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cpu->env_ptr;
@ -13288,11 +13288,9 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
if (dc->ss_active) {
bound = 1;
}
max_insns = MIN(max_insns, bound);
dc->base.max_insns = MIN(dc->base.max_insns, bound);
init_tmp_a64_array(dc);
return max_insns;
}
static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)

9
target/arm/translate.c
View file

@ -12243,8 +12243,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
return !thumb_insn_is_16bit(s, insn);
}
static int arm_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cs, int max_insns)
static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cs->env_ptr;
@ -12305,14 +12304,14 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,
/* If architectural single step active, limit to 1. */
if (is_singlestepping(dc)) {
max_insns = 1;
dc->base.max_insns = 1;
}
/* ARM is a fixed-length ISA. Bound the number of insns to execute
to those left on the page. */
if (!dc->thumb) {
int bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
max_insns = MIN(max_insns, bound);
dc->base.max_insns = MIN(dc->base.max_insns, bound);
}
cpu_F0s = tcg_temp_new_i32();
@ -12323,8 +12322,6 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,
cpu_V1 = cpu_F1d;
/* FIXME: cpu_M0 can probably be the same as cpu_V0. */
cpu_M0 = tcg_temp_new_i64();
return max_insns;
}
static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)

7
target/hppa/translate.c
View file

@ -4669,8 +4669,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
return gen_illegal(ctx);
}
static int hppa_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cs, int max_insns)
static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
int bound;
@ -4700,14 +4699,12 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase,
/* Bound the number of instructions by those left on the page. */
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
bound = MIN(max_insns, bound);
ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
ctx->ntempr = 0;
ctx->ntempl = 0;
memset(ctx->tempr, 0, sizeof(ctx->tempr));
memset(ctx->templ, 0, sizeof(ctx->templ));
return bound;
}
static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)

5
target/i386/translate.c
View file

@ -8402,8 +8402,7 @@ void tcg_x86_init(void)
}
}
static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,
int max_insns)
static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUX86State *env = cpu->env_ptr;
@ -8470,8 +8469,6 @@ static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,
cpu_ptr0 = tcg_temp_new_ptr();
cpu_ptr1 = tcg_temp_new_ptr();
cpu_cc_srcT = tcg_temp_local_new();
return max_insns;
}
static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu)

5
target/ppc/translate.c
View file

@ -7215,8 +7215,7 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
#endif
}
static int ppc_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cs, int max_insns)
static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUPPCState *env = cs->env_ptr;
@ -7281,7 +7280,7 @@ static int ppc_tr_init_disas_context(DisasContextBase *dcbase,
#endif
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
return MIN(max_insns, bound);
ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
}
static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)