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target/riscv: rvv-1.0: Add Zve64f extension into RISC-V

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Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-01-18 09:45:04 +08:00 • committed by Alistair Francis
parent 22599b795c
commit b4a99d4027
5 changed files with 16 additions and 2 deletions
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5
target/riscv/cpu_helper.c
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@ -69,12 +69,15 @@ static RISCVMXL cpu_get_xl(CPURISCVState *env)
void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
uint32_t flags = 0;
*pc = env->pc;
*cs_base = 0;
if (riscv_has_ext(env, RVV)) {
if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
/*
* If env->vl equals to VLMAX, we can use generic vector operation
* expanders (GVEC) to accerlate the vector operations.