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https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 15:53:54 -06:00
CRIS updates:
* Support both the I and D MMUs and improve the accuracy of the MMU model. * Handle the automatic user/kernel stack pointer switching when leaving or entering user mode. * Move the CCS evaluation into helper funcs. * Make sure user-mode cannot change flags only writeable in kernel mode. * More conversion of the translator into TCG. * Handle exceptions while in a delayslot. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4299 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
ff56ff7a07
commit
b41f7df018
9 changed files with 938 additions and 639 deletions
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@ -73,11 +73,30 @@ static inline void set_field(uint32_t *dst, unsigned int val,
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val <<= offset;
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val &= mask;
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D(printf ("val=%x mask=%x dst=%x\n", val, mask, *dst));
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*dst &= ~(mask);
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*dst |= val;
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}
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static void dump_tlb(CPUState *env, int mmu)
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{
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int set;
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int idx;
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uint32_t hi, lo, tlb_vpn, tlb_pfn;
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for (set = 0; set < 4; set++) {
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for (idx = 0; idx < 16; idx++) {
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lo = env->tlbsets[mmu][set][idx].lo;
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hi = env->tlbsets[mmu][set][idx].hi;
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tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
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tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
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set, idx, hi, lo, tlb_vpn, tlb_pfn);
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}
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}
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}
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/* rw 0 = read, 1 = write, 2 = exec. */
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static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
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CPUState *env, uint32_t vaddr,
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int rw, int usermode)
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@ -88,53 +107,63 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
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uint32_t tlb_vpn, tlb_pfn = 0;
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int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
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int cfg_v, cfg_k, cfg_w, cfg_x;
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int i, match = 0;
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int set, match = 0;
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uint32_t r_cause;
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uint32_t r_cfg;
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int rwcause;
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int update_sel = 0;
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int mmu = 1; /* Data mmu is default. */
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int vect_base;
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r_cause = env->sregs[SFR_R_MM_CAUSE];
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r_cfg = env->sregs[SFR_RW_MM_CFG];
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rwcause = rw ? CRIS_MMU_ERR_WRITE : CRIS_MMU_ERR_READ;
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switch (rw) {
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case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
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case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
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default:
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case 0: rwcause = CRIS_MMU_ERR_READ; break;
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}
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/* I exception vectors 4 - 7, D 8 - 11. */
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vect_base = (mmu + 1) * 4;
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vpage = vaddr >> 13;
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idx = vpage & 15;
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/* We know the index which to check on each set.
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Scan both I and D. */
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#if 0
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for (i = 0; i < 4; i++) {
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int j;
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for (j = 0; j < 16; j++) {
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lo = env->tlbsets[1][i][j].lo;
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hi = env->tlbsets[1][i][j].hi;
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for (set = 0; set < 4; set++) {
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for (idx = 0; idx < 16; idx++) {
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lo = env->tlbsets[mmu][set][idx].lo;
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hi = env->tlbsets[mmu][set][idx].hi;
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tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
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tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
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i, j, hi, lo, tlb_vpn, tlb_pfn);
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set, idx, hi, lo, tlb_vpn, tlb_pfn);
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}
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}
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#endif
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for (i = 0; i < 4; i++)
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idx = vpage & 15;
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for (set = 0; set < 4; set++)
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{
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lo = env->tlbsets[1][i][idx].lo;
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hi = env->tlbsets[1][i][idx].hi;
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lo = env->tlbsets[mmu][set][idx].lo;
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hi = env->tlbsets[mmu][set][idx].hi;
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tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
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tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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D(printf ("TLB[%d][%d] tlbv=%x vpage=%x -> pfn=%x\n",
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i, idx, tlb_vpn, vpage, tlb_pfn));
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D(printf("TLB[%d][%d] v=%x vpage=%x -> pfn=%x lo=%x hi=%x\n",
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i, idx, tlb_vpn, vpage, tlb_pfn, lo, hi));
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if (tlb_vpn == vpage) {
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match = 1;
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break;
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}
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}
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res->bf_vec = vect_base;
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if (match) {
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cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
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cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
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cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
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@ -158,54 +187,67 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
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set_exception_vector(0x0a, d_mmu_access);
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set_exception_vector(0x0b, d_mmu_write);
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*/
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if (cfg_v && !tlb_v) {
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printf ("tlb: invalid\n");
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if (!tlb_g
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&& tlb_pid != (env->pregs[PR_PID] & 0xff)) {
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D(printf ("tlb: wrong pid %x %x pc=%x\n",
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tlb_pid, env->pregs[PR_PID], env->pc));
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match = 0;
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res->bf_vec = vect_base;
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} else if (rw == 1 && cfg_w && !tlb_w) {
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D(printf ("tlb: write protected %x lo=%x\n",
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vaddr, lo));
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match = 0;
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res->bf_vec = vect_base + 3;
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} else if (cfg_v && !tlb_v) {
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D(printf ("tlb: invalid %x\n", vaddr));
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set_field(&r_cause, rwcause, 8, 9);
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match = 0;
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res->bf_vec = 0x9;
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update_sel = 1;
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res->bf_vec = vect_base + 1;
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}
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else if (!tlb_g
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&& tlb_pid != 0xff
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&& tlb_pid != env->pregs[PR_PID]
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&& cfg_w && !tlb_w) {
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printf ("tlb: wrong pid\n");
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match = 0;
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res->bf_vec = 0xa;
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}
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else if (rw && cfg_w && !tlb_w) {
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printf ("tlb: write protected\n");
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match = 0;
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res->bf_vec = 0xb;
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}
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} else
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update_sel = 1;
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if (update_sel) {
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/* miss. */
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env->sregs[SFR_RW_MM_TLB_SEL] = 0;
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D(printf ("tlb: miss %x vp=%x\n",
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env->sregs[SFR_RW_MM_TLB_SEL], vpage & 15));
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set_field(&env->sregs[SFR_RW_MM_TLB_SEL], vpage & 15, 0, 4);
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set_field(&env->sregs[SFR_RW_MM_TLB_SEL], 0, 4, 5);
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res->bf_vec = 0x8;
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res->prot = 0;
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if (match) {
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res->prot |= PAGE_READ;
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if (tlb_w)
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res->prot |= PAGE_WRITE;
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if (tlb_x)
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res->prot |= PAGE_EXEC;
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}
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else
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D(dump_tlb(env, mmu));
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env->sregs[SFR_RW_MM_TLB_HI] = hi;
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env->sregs[SFR_RW_MM_TLB_LO] = lo;
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}
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if (!match) {
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set_field(&r_cause, rwcause, 8, 9);
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/* miss. */
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idx = vpage & 15;
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set = 0;
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/* Update RW_MM_TLB_SEL. */
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env->sregs[SFR_RW_MM_TLB_SEL] = 0;
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set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
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set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 5);
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/* Update RW_MM_CAUSE. */
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set_field(&r_cause, rwcause, 8, 2);
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set_field(&r_cause, vpage, 13, 19);
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set_field(&r_cause, env->pregs[PR_PID], 0, 8);
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env->sregs[SFR_R_MM_CAUSE] = r_cause;
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D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
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}
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D(printf ("%s mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
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" %x cause=%x sel=%x r13=%x\n",
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__func__, match, env->pc,
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D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
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" %x cause=%x sel=%x sp=%x %x %x\n",
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__func__, rw, match, env->pc,
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vaddr, vpage,
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tlb_vpn, tlb_pfn, tlb_pid,
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env->pregs[PR_PID],
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r_cause,
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env->sregs[SFR_RW_MM_TLB_SEL],
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env->regs[13]));
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env->regs[R_SP], env->pregs[PR_USP], env->ksp));
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res->pfn = tlb_pfn;
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return !match;
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@ -236,10 +278,17 @@ int cris_mmu_translate(struct cris_mmu_result_t *res,
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int seg;
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int miss = 0;
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int is_user = mmu_idx == MMU_USER_IDX;
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uint32_t old_srs;
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old_srs= env->pregs[PR_SRS];
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/* rw == 2 means exec, map the access to the insn mmu. */
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env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
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if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
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res->phy = vaddr;
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return 0;
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res->prot = PAGE_BITS;
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goto done;
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}
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seg = vaddr >> 28;
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@ -251,17 +300,16 @@ int cris_mmu_translate(struct cris_mmu_result_t *res,
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base = cris_mmu_translate_seg(env, seg);
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phy = base | (0x0fffffff & vaddr);
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res->phy = phy;
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res->prot = PAGE_BITS;
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}
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else
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{
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miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
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if (!miss) {
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phy &= 8191;
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phy |= (res->pfn << 13);
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res->phy = phy;
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}
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phy = (res->pfn << 13);
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res->phy = phy;
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}
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D(printf ("miss=%d v=%x -> p=%x\n", miss, vaddr, phy));
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done:
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env->pregs[PR_SRS] = old_srs;
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return miss;
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}
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#endif
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