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hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

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Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241120153935.24706-2-jim.shu@sifive.com>
[ Changes by AF
 -  Store fdt_load_addr_hi32 in the reset vector
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Jim Shu 2024-11-20 23:39:33 +08:00 • committed by Alistair Francis
parent d2ed9fffba
commit b4132a9e62
6 changed files with 20 additions and 14 deletions
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4
hw/riscv/microchip_pfsoc.c
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@ -519,7 +519,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
bool kernel_as_payload = false;
target_ulong firmware_end_addr, kernel_start_addr;
uint64_t kernel_entry;
uint32_t fdt_load_addr;
uint64_t fdt_load_addr;
DriveInfo *dinfo = drive_get(IF_SD, 0, 0);
/* Sanity check on RAM size */
@ -625,7 +625,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
memmap[MICROCHIP_PFSOC_DRAM_LO].size,
machine);
machine, &s->soc.u_cpus);
riscv_load_fdt(fdt_load_addr, machine->fdt);
/* Load the reset vector */